Flash Storage Pipeline Without Lower-Level Controllers

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Solution Overview

Problem

Existing storage systems face inefficiencies in managing data operations, particularly in flash storage systems, where lower-level processes often perform redundant tasks, leading to reduced reliability and increased latency.

Innovation Solution

Implementing a direct-mapped flash storage system where higher-level processes manage data operations directly, eliminating the need for lower-level storage controllers, and utilizing non-volatile RAM for data buffering to enhance write performance and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If lower-level storage controllers are used to manage data operations, then device complexity is reduced, but reliability decreases due to redundant tasks and increased latency

Engineering Contradiction:
Improvedata operation reliabilityVSAvoidstorage system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the lower-level storage controller from the data path, allowing higher-level processes to manage data operations directly. This eliminates the redundant task of multiple controllers performing overlapping functions, thereby improving reliability while reducing overall system complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The storage system is designed to be self-managing at the higher-level process, where data operations are handled directly by the storage system itself rather than being mediated through additional controller layers. This self-service approach reduces latency and eliminates redundant processing steps.

Inventive Principle:
Principle #25Self-service

2Speed

If traditional storage controllers are used, then ease of operation is maintained, but latency increases due to redundant operations

Engineering Contradiction:
Improvedata operation speedVSAvoidoperation latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

By removing the lower-level storage controller from the data operation path, the patent eliminates the time-consuming redundant processing that occurs when multiple controllers handle the same data operations, directly reducing latency and improving operation speed.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent enables higher-level processes to skip the intermediate storage controller layer and directly manage data operations, rushing through the critical path of data handling to minimize latency and maximize speed.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If non-volatile RAM is used for data buffering, then reliability is improved during power failures, but device complexity increases

Engineering Contradiction:
Improvepower failure reliabilityVSAvoidbuffering system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the physical state parameter of the buffering medium by using non-volatile RAM instead of traditional volatile memory or disk-based buffering. This parameter change provides persistence during power failures while maintaining the buffering function, improving reliability without requiring complex hybrid storage architectures.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260056947A1Real-time data analytics and pipeline optimization in storage systems
Publication Date: 2026.02.26 PURE STORAGE INC
  • US20260056947A1 patent drawing
  • US20260056947A1 patent drawing
  • US20260056947A1 patent drawing

AI summary

A dataset is received from a data source. A real-time analytics operation is executed on at least a portion of the dataset prior to fully persisting the dataset. Results of the real-time analytics operation are stored.