Multi-Level Flash Storage Read Latency Reduction
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Solution Overview
Problem
Flash memory technologies like MLC, TLC, and QLC suffer from higher read latencies due to the need for multiple voltage thresholds, which is a limitation in applications requiring low latency and high memory density, such as enterprise data storage and cache flash appliances.
Innovation Solution
A memory system with a controller that encodes data in multi-level flash storage devices to enable reading data using a single voltage threshold, reducing read latency by organizing data in a way that allows for efficient retrieval across multiple levels without applying multiple voltage thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple voltage thresholds are applied to read MLC, TLC, or QLC flash memory, then data can be correctly detected from multi-level cells, but read latency increases significantly
Solution Approach 1:
The flash memory array is divided into multiple independent planes, where each plane can be read using a single voltage threshold. By segmenting the multi-level cell data across multiple planes, the system enables parallel read operations that reduce overall read latency while maintaining data detection accuracy through single-threshold comparisons in each plane.
Solution Approach 2:
The patent introduces a plane dimension to the traditional single-threshold read architecture. By organizing data in a three-dimensional structure (rows, columns, and planes) and enabling simultaneous reads across multiple planes with different voltage thresholds, the system achieves both high data detection accuracy and reduced read latency through dimensional expansion of the read operation.
2Quantity of substance
If MLC, TLC, or QLC flash memory is used to increase memory density, then storage capacity improves, but read latency becomes unacceptable for latency-sensitive applications
Solution Approach 1:
The multi-level cell data is segmented across multiple planes, allowing the system to maintain high memory density while enabling parallel read operations. Each plane contains a portion of the multi-level data that can be read independently with a single voltage threshold, effectively dividing the latency-critical path into parallel segments.
Solution Approach 2:
Data is pre-organized during the write operation into a multi-plane structure that facilitates single-threshold reads. By preliminarily distributing multi-level cell data across multiple planes during programming, the system prepares the data in advance for rapid retrieval using simplified single-threshold read operations, reducing read latency without sacrificing memory density.
Data Source
AI summary
A memory system, non-volatile solid-state memory, and a method of efficiently reading data from a flash memory array are disclosed. The disclosed memory system includes a flash memory array having a plurality of memory cells that store data therein, each of the plurality of memory cells being configured to store at least two bits per cell and being organized into pages, and a controller configured to read any bit of data from a page of the flash memory array by applying a single threshold voltage to the flash memory array. Reading data from the flash memory array with a single threshold greatly decreases the latency associated with the read operation.