Flash Storage Block Management via Shallow Erase and ISPP
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Solution Overview
Problem
Flash memory storage systems face reduced endurance due to repeated programming and erasing cycles, leading to errors that cannot be corrected, which limits their usage and requires methods like wear leveling and block reuse, but these methods reduce storage capacity and are not suitable for applications allowing data quality degradation.
Innovation Solution
A method that sorts flash storage blocks by erase modes and allocates them based on error rates, using shallow erase techniques and incremental step pulse programming to reduce cell damage, thereby extending the lifetime of the storage system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If conventional wear leveling and block reuse methods are used to extend flash memory lifetime, then the endurance is improved, but the storage capacity is reduced
Solution Approach 1:
The patent changes the parameter of erase voltage by introducing shallow erase (reducing erase voltage to 1/2 or 1/3 of normal voltage) to reduce cell damage during erase operations. This allows blocks to be reused more times without exceeding P/E cycle limits, extending flash memory lifetime while maintaining storage capacity by avoiding aggressive block replacement strategies
2Reliability
If aggressive wear leveling is applied to prevent premature block failure, then reliability is improved, but storage capacity is reduced
Solution Approach 1:
The patent applies different erase strategies to different blocks based on their usage patterns and error rates. Frequently accessed blocks receive shallow erase treatment to minimize damage, while less accessed blocks use normal erase. This localized approach maintains reliability for active blocks while preserving storage capacity by not unnecessarily retiring blocks
3Reliability
If blocks are discarded upon single uncorrectable error to ensure data integrity, then reliability is improved, but storage capacity is reduced
Solution Approach 1:
The patent changes the error tolerance parameter by introducing imprecise blocks that allow a certain number of uncorrectable errors (e.g., 1-3 errors) before block retirement. This relaxation of the error threshold enables continued use of blocks that would otherwise be discarded, maintaining data integrity at an acceptable level while significantly preserving storage capacity
4Duration of action of stationary object
If shallow erase is applied to reduce cell damage, then flash memory lifetime is extended, but data precision is reduced
Solution Approach 1:
The patent creates different block quality levels: precise blocks using normal erase for high-reliability data and imprecise blocks using shallow erase for error-tolerant data. This local quality differentiation allows shallow erase to extend lifetime for appropriate applications while maintaining data precision where required
Solution Approach 2:
The patent introduces a data precision parameter that allows applications to specify their error tolerance requirements. Based on this parameter, the system selects appropriate erase modes and block allocation strategies, enabling a trade-off between lifetime extension and data precision that is controlled and application-specific
Data Source
AI summary
A managing method for a flash storage includes: sorting a plurality of blocks within the flash storage into precise blocks and imprecise blocks; and managing the sorted blocks as a plurality of free block pools. The management includes performing garbage collection and wear leveling, and the wear leveling is performed based on CEW (Cumulative Effective Wearing), the CEW indicating cumulative cell damage induced by performing a plurality of operations on a specific block. A storage system includes a memory array; and a memory controller sorting a plurality of blocks of the memory array based on error rates, applying erase voltages corresponding to the error rates, respectively, when data stored in the blocks are erased, controlling each of the erase voltages to have a value scaled down from a standard voltage, and performing incremental step pulse programming on one or more of the blocks.