Flash Storage Control for Write-Time Variation and Staggered Erase

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Solution Overview

Problem

Flash memory devices face challenges in data write times varying across word lines due to structural differences, leading to inconsistent quality of service (QoS) when allocated the same time for data operations.

Innovation Solution

A storage device with a splitter that determines the longest write time as a reference time, allowing for the erase operation to be divided and performed during the remaining time of each word line, ensuring consistent QoS by hiding I/O latency through staggered erase operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the flash memory device allocates the same time for data writing to all word lines, then the quality of service (QoS) allocation is uniform, but the actual write completion times vary due to different word line characteristics

Engineering Contradiction:
ImproveQoS consistencyVSAvoidwrite time variation
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller pre-obtains write times for each word line and determines a reference time (longest write time) before actual data writing occurs. This preliminary characterization allows the system to allocate appropriate time resources and schedule erase operations in advance, ensuring that shorter-write word lines can complete their writes before the reference time and have their remaining time utilized for erase operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the flash memory device performs erase operations separately after write operations, then data integrity is maintained, but overall operation latency increases

Engineering Contradiction:
Improvedata integrityVSAvoidoperation latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller determines and commands erase operations in advance based on pre-obtained write time information. By calculating the reference time and identifying which word lines will complete writing before this reference time, the controller can schedule erase operations to begin during the write operation itself, rather than waiting for all writes to complete. This preliminary scheduling maintains data integrity while reducing overall latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system performs erase operations continuously during the write operation by utilizing the remaining time of word lines that complete writing before the reference time. Instead of having idle periods after write completion, the erase operation continues seamlessly using the time that would otherwise be wasted, thereby maintaining continuous useful action and reducing total operation time.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If the flash memory device waits for all word lines to complete writing before performing erase operations, then data consistency is ensured, but productivity decreases

Engineering Contradiction:
Improvedata consistencyVSAvoidoperation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The controller pre-obtains write time characteristics for each word line and determines a reference time before actual operations. This preliminary information allows the controller to identify which word lines will complete writing before the reference time and schedule erase operations accordingly, rather than waiting for all writes to complete. This ensures data consistency for word lines that haven't completed writing yet while improving productivity by performing erases early.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller divides word lines into different groups based on their write time characteristics relative to the reference time. Word lines that complete writing before the reference time are segmented for early erase operations, while word lines that complete at or after the reference time wait for proper timing. This segmentation allows simultaneous progression of write and erase operations on different word lines, improving overall productivity while maintaining data consistency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12386535B2Storage device, electronic device, and method for controlling memory
Publication Date: 2025.08.12 SAMSUNG ELECTRONICS CO LTD
  • US12386535B2 patent drawing
  • US12386535B2 patent drawing
  • US12386535B2 patent drawing

AI summary

A storage device includes: a non-volatile memory configured to include a plurality of blocks having a plurality of word lines and to write data to the blocks or to erase data of the blocks; and a splitter configured to obtain write times for a plurality of word lines of a first block of the blocks while the non-volatile memory writes data in the first block, and to command the non-volatile memory to perform an erase operation on a second block of the blocks by the reference time when a write time for one of the word lines is shorter than the reference time.