Split-Gate Flash Strap Cell Layout to Prevent Source-Line Shorting
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Solution Overview
Problem
Existing split-gate flash memory cells require a source line contact on the strap cell between two adjacent control gate lines, leading to potential shorting between the erase gate line and the source line.
Innovation Solution
A semiconductor memory device design with an asymmetric active area layout and continuous erase gate line, featuring a strap cell with a dummy floating gate and always-on floating gate channel, and a source line contact aligned with bit line contacts, avoiding direct openings above the strap cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a source line contact is provided on the strap cell between two adjacent control gate lines, then the memory cell structure can be completed, but shorting between the erase gate line and the source line occurs
Solution Approach 1:
The source line contact is repositioned from a location between control gate lines to a location beneath the select gate line, changing the spatial dimension of contact placement. This dimensional shift allows the source line contact to connect to the diffusion region without intersecting the erase gate line, thereby preventing shorting while maintaining structural completeness
Solution Approach 2:
The strap cell employs an asymmetric active area layout where the source line contact is positioned at a specific asymmetric location beneath the select gate line rather than symmetrically between control gate lines. This asymmetric configuration optimizes the spatial relationship between contacts and gate lines, preventing shorting between the erase gate line and source line contact
2Reliability
If the erase gate line is continuous through the strap cell, then shorting is prevented, but the injection efficiency may be reduced
Solution Approach 1:
The gate dielectric layer thickness is varied locally: it is thicker in regions where the erase gate line is continuous (beneath the select gate line) to prevent shorting, and can be optimized in other regions to maintain injection efficiency. This local variation in dielectric quality allows simultaneous achievement of reliability and productivity
Solution Approach 2:
The diffusion region acts as an intermediary structure that receives the source line contact beneath the select gate line, allowing electrical connection without requiring the erase gate line to be discontinuous. This intermediary approach maintains the continuity of the erase gate line for reliability while preserving injection efficiency through proper contact positioning
Data Source
AI summary
A semiconductor memory device includes device lines comprising a select gate (SG) line, a control gate (CG) line, an erase gate (EG) line, and a source line elongated in parallel along a first direction. The CG line is disposed between the EG line and the SG line, and the source line underlies the EG line in the substrate. The plurality of device lines defines memory cells and at least one strap cell between the memory cells spaced along lengths of the device lines. Bit line (BL) contacts are electrically connected to drain doped regions of the memory cells respectively. The drain doped regions is adjacent to the SG line. At least one source line contact is electrically connected to a diffusion region of the strap cell under the SG line. The EG line continuously passes through the strap cell.