Flash Memory Sub-Data Checking for Faster Small Reads

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Solution Overview

Problem

The data access efficiency of flash memory storage systems is reduced due to the need to read and correct entire pages of data, even when only small amounts of data are accessed, as existing error correction codes require reading the entire page to verify data integrity.

Innovation Solution

A data access method that generates a bit checking code for each sub-data unit, allowing for efficient verification of small data reads without needing to read the entire page, thereby improving access efficiency by determining if error bits are present before executing a full error correction procedure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the flash memory storage system generates ECC for multiple sectors in a page, then the error correction capability is improved, but the data access efficiency deteriorates when reading small data

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddata access efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the error checking mechanism into two levels: a first error checking circuit that checks all data in a page using ECC, and a second error checking circuit that checks only specific sub-data units (sectors) using a separately stored checking code. This segmentation allows the system to perform quick checks on small data accesses without reading the entire page, thus resolving the contradiction between error correction capability and data access efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-calculating and storing a checking code for each sub-data unit (sector) in the page along with the data. When a small data access occurs, the system first performs a quick check using the pre-stored checking code before deciding whether to read the entire page and apply full ECC correction. This preliminary check avoids unnecessary full-page reads and improves access efficiency while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If the flash memory page size is increased to store more data, then the storage capacity is improved, but the error correction overhead increases

Engineering Contradiction:
Improvestorage capacityVSAvoiderror correction overhead
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the error correction overhead into two parts: a first checking code (ECC) stored once per page that covers all data in the page, and second checking codes stored once per sub-data unit that enable quick verification of small data accesses. This segmentation reduces the effective overhead for small data operations while maintaining the storage capacity benefits of larger page sizes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by performing error checking only on the specific sub-data unit that is being accessed, rather than checking the entire page. The system uses the pre-stored checking code for the accessed sector to determine if error correction is needed, avoiding the excessive action of reading and checking all data in the page when only a small portion is required.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20100262892A1Data access method for flash meory and storage system and controller thereof
Publication Date: 2010.10.14 PHISON ELECTRONICS
  • US20100262892A1 patent drawing
  • US20100262892A1 patent drawing
  • US20100262892A1 patent drawing

AI summary

A data access method for accessing data in a flash memory is provided, wherein the data has a plurality of sub-data. The data access method includes generating an error correction code (ECC) for the data and writing the data and the ECC into the flash memory. The data access method also includes generating a corresponding bit checking code for each of the sub-data and writing the bit checking codes into the flash memory. When the sub-data subsequently is read from the flash memory, whether the sub-data contains any error is determined only according to the bit checking code corresponding to the sub-data. Thereby, the data access efficiency is improved.