Flash Device Endurance Test Method Using Synchronous Pulse Signals
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Solution Overview
Problem
Conventional flash device endurance test methods are time-consuming due to the need for repeated hardware connections and reconfiguration of voltage conditions during erasing and writing cycles, significantly prolonging the test process.
Innovation Solution
A flash device endurance test method where ports of the same test condition are connected to the same pulse generation unit, generating synchronous pulse voltage signals for repeated erasing-writing cycles, reducing the need for frequent hardware reconnection and optimizing test efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware connection is re-performed before each erasing or writing operation, then voltage conditions can be correctly applied, but test time is significantly prolonged
Solution Approach 1:
The patent pre-configures multiple pulse generation units with different voltage conditions before testing begins. Each unit is prepared in advance with specific voltage parameters (e.g., erase voltage, write voltage, read voltage) so that when testing starts, no time-consuming reconnection or reconfiguration is needed during the actual erasing and writing operations.
Solution Approach 2:
The patent implements periodic testing cycles where multiple memory cells are subjected to erasing and writing operations in a repeating sequence. By using pre-configured pulse generation units, the system can maintain continuous periodic operation without interruptions for hardware reconnection, thereby significantly reducing total test time while ensuring accurate voltage application throughout all cycles.
2Adaptability or versatility
If ports are connected to different pulse generation units for different test conditions, then voltage flexibility is improved, but device complexity and connection management become more complex
Solution Approach 1:
The patent divides the test system into multiple independent pulse generation units, each responsible for generating specific voltage conditions (erase, write, read). This segmentation allows each unit to be optimized for its specific function while reducing the complexity of any single unit. Memory cells are also segmented into groups, with each group connected to a specific pulse generation unit, simplifying the overall connection architecture.
Solution Approach 2:
The patent designs pulse generation units that can serve multiple functions within their assigned groups. Each unit is capable of generating various voltage levels and waveforms needed for different operations (erase, write, read) on its connected memory cells. This multi-functionality reduces the need for specialized equipment for each operation type, simplifying the overall test system while maintaining voltage flexibility.
Data Source
AI summary
A flash device endurance test method is provided. A flash device to be tested, which has a plurality of memory cells, includes multiple ports with the same and different test conditions. The method includes connecting the ports of the same test condition to the same pulse generation unit, and connecting the ports of different test conditions to different pulse generation units; generating by all of the pulse generation units, synchronous pulse voltage signals of N cycles, wherein one time of erasing-writing of the flash device is considered to be one of the cycles; and testing threshold voltages of erasing and writing states in each cycle.