Flash Memory Read Threshold Control for Charge Distribution Drift
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Solution Overview
Problem
Flash memory systems face challenges in accurately reading data due to disturbances in electric charge distributions caused by program/erase cycles and data retention, leading to incorrect threshold voltage settings and unsuccessful codeword error corrections.
Innovation Solution
A memory controller with a control logic circuit, receiving circuit, and data processing circuit that selects an initial gate voltage combination, performs codeword error correction, and determines an electric charge distribution parameter, using a look-up table to find a target gate voltage combination for accurate data reading, thereby reducing the need for individual testing of voltage combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fixed threshold voltage reading methods are used, then the reading process is simple, but reading accuracy deteriorates due to electric charge distribution changes from program/erase cycles and data retention
Solution Approach 1:
The patent implements dynamic threshold voltage adjustment by continuously tracking electric charge distribution changes in flash memory cells. Instead of using fixed threshold voltages, the system adapts the reading threshold voltages based on detected charge distribution patterns, thereby maintaining high reading accuracy despite program/erase cycle effects and data retention challenges
Solution Approach 2:
The patent employs feedback mechanisms where the reading process itself provides information about actual charge distributions. By analyzing reading results and comparing against expected patterns, the system adjusts threshold voltages for subsequent readings, creating a closed-loop system that improves accuracy while managing complexity through intelligent control
2Measurement precision
If individual testing of voltage combinations is performed to find optimal reading voltages, then reading accuracy improves, but reading time increases significantly
Solution Approach 1:
The patent performs preliminary tracking of electric charge distributions during programming and erasing operations. By detecting charge distribution patterns at these earlier stages, the system pre-determines appropriate threshold voltages for subsequent reading operations, eliminating the need for time-consuming individual voltage testing during actual data retrieval
Solution Approach 2:
The patent skips the traditional time-consuming process of individually testing multiple voltage combinations by using a simplified voltage selection method based on detected charge distribution patterns. This allows the system to rapidly identify appropriate reading voltages without exhaustive testing, thereby maintaining high reading speed while ensuring accuracy
3Reliability
If fixed gate voltage combinations are used for reading, then the control process is simple, but error correction fails when charge distributions change
Solution Approach 1:
The patent implements dynamic gate voltage combination selection that adapts to changing charge distributions. Instead of using fixed voltage combinations, the system adjusts the gate voltage combinations based on detected electric charge patterns, ensuring that reading operations remain synchronized with actual memory cell states and improving error correction success rates
Solution Approach 2:
The patent uses feedback from reading operations to determine whether charge distribution changes have occurred. When changes are detected, the system adjusts gate voltage combinations accordingly, creating an adaptive control mechanism that improves reliability while managing complexity through intelligent, condition-based control logic
Data Source
AI summary
An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.