Adjustable Flash Translation Layer for Address Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash translation layers face inefficiencies in managing flash memory due to block-level addressing, leading to increased null data collection procedures and reduced operation speed, especially as flash memory volume grows.
Innovation Solution
An adjustable flash translation layer with a coarse-grained and fine-grained address translation table, along with a cache instruction-data register, is introduced to enhance address conversion efficiency and reduce null data collection occurrences by caching address converting data and instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If block-level addressing is used in flash translation layer, then flash memory can be managed with original file system, but null data collection procedures increase and operation speed decreases
Solution Approach 1:
The patent segments the address translation into two levels: coarse-grained block-level translation for high-level file system compatibility, and fine-grained page-level translation for efficient data access. This segmentation allows the system to maintain compatibility with original file systems while improving operation speed through optimized page-level management.
Solution Approach 2:
The patent introduces a fine-grained page-level address translation table as an additional dimension to the existing block-level translation. This two-dimensional translation mechanism (block level + page level) resolves the contradiction by adding granularity without sacrificing compatibility.
2Device complexity
If block-level addressing is used, then flash memory structure is simplified, but null data collection frequency increases
Solution Approach 1:
The patent divides the address translation into coarse-grained block-level and fine-grained page-level segments. The fine-grained page-level table tracks individual page status, enabling the system to identify and collect only truly null pages rather than entire blocks, reducing null data collection frequency while maintaining structured management.
Solution Approach 2:
The fine-grained page-level address translation table performs preliminary tracking of page usage status before null data collection is needed. By maintaining continuous information about which pages are actually null, the system can perform more accurate and less frequent null data collection operations.
3Speed
If coarse-grained address translation table is used, then address conversion is faster, but space requirements increase for null data collection
Solution Approach 1:
The patent segments the translation table into coarse-grained block-level entries for fast initial mapping and fine-grained page-level entries for precise tracking. This segmentation allows the system to use smaller, more efficient data structures at the page level compared to a single large fine-grained table, reducing overall space requirements while maintaining fast address conversion.
Solution Approach 2:
The system uses partial fine-grained tracking only for pages that require individual management, rather than implementing complete fine-grained tracking for all blocks. This selective approach reduces the quantity of data stored in the translation structure while maintaining sufficient speed for address conversion operations.
Data Source
AI summary
A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.