Flash Translation Layer Wear Leveling for NAND Retention

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Solution Overview

Problem

NAND flash memory retention characteristics degrade and service life shortens due to frequent and unbalanced erase processes, leading to reduced data retention as the number of rewrite operations increases, especially when erase intervals are short.

Innovation Solution

A memory system with a block controller that measures erase times, detects blocks with short rewrite periods, and performs data leveling by moving data from blocks in use with old erase times to free blocks with older erase times, thereby balancing erase counts and extending the service life.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data items are sequentially recorded in addresses specified from the exterior, then data recording efficiency is improved, but rewrite processes become concentrated in specified regions causing unbalanced erase counts

Engineering Contradiction:
Improvedata recording efficiencyVSAvoiderase count balance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an address translation layer (FTL - Flash Translation Layer) that acts as an intermediary between the host system and the physical flash memory blocks. This translation layer maps logical addresses to physical block addresses, enabling the system to record data sequentially from the host perspective while distributing actual write operations across multiple physical blocks. The translation layer maintains mapping tables that track which logical addresses correspond to which physical blocks, allowing efficient address management without concentrating erase operations in specific regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the flash memory storage space into multiple logical blocks and physical blocks, where one logical block may span multiple physical blocks. This segmentation allows the system to manage data at the logical block level while performing operations at the physical block level. When a logical block needs to be erased, the system can selectively erase only the necessary physical blocks rather than concentrating erases in a single region, thus distributing wear across the storage medium.

Inventive Principle:
Principle #1Segmentation

2Reliability

If erase processes are performed frequently to maintain data integrity, then data retention is improved, but service life shortens due to gate oxide film degradation

Engineering Contradiction:
Improvedata retentionVSAvoidservice life
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent implements wear leveling algorithms that dynamically adjust erase operation parameters based on the historical erase count of each physical block. The system tracks erase frequencies and identifies blocks that have undergone fewer erase operations, then prioritizes selecting these blocks for upcoming erase operations. This parameter-based management ensures that erase operations are distributed evenly across all blocks, preventing any single block from experiencing excessive erases that would cause gate oxide film degradation and reduce service life.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary assessment of block wear status before initiating erase operations. The system maintains records of erase counts for each physical block and uses this information to pre-determine which blocks are suitable for upcoming erase operations. By planning erase operations in advance based on wear distribution, the system可以避免集中擦除导致的寿命缩短,同时确保数据完整性得到维护。

Inventive Principle:
Principle #10Preliminary action

3Productivity

If erase interval is shortened to increase rewrite operations, then productivity is improved, but retention characteristic degrades

Engineering Contradiction:
Improverewrite operation speedVSAvoidretention characteristic
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a time dimension to the erase operation management by implementing a timing-based wear leveling mechanism. The system not only considers the spatial distribution of erase operations across blocks but also monitors the temporal intervals between erases for each block. By tracking the time elapsed since the last erase operation, the system ensures that subsequent erase operations are scheduled with appropriate intervals, preventing retention characteristic degradation even when rewrite operations are performed at high speeds.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7958411B2Memory system and control method thereof
Publication Date: 2011.06.07 KIOXIA CORP
  • US7958411B2 patent drawing
  • US7958411B2 patent drawing
  • US7958411B2 patent drawing

AI summary

A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.