Flash Translation Layer Random Write Page Mapping
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Solution Overview
Problem
Flash memory systems face challenges in being used as main memory or general hard disk filing systems due to their erase-before-write operation characteristic, which complicates their application and requires the use of a flash translation layer (FTL) for address mapping to recognize them as hard disks or SRAM, but existing FTLs lack efficient management of random write operations.
Innovation Solution
A memory system with an interface device that stores a flash translation layer using a data block mapping table, a log block mapping table, and a page mapping table, which converts data blocks into random write blocks when necessary, employing a random write page mapping table independent from the others to manage random write operations effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a flash translation layer (FTL) with address mapping table is used to make flash memory recognizable as hard disk or SRAM, then the adaptability of flash memory improves, but the device complexity increases due to the need for additional mapping tables and translation mechanisms
Solution Approach 1:
The patent divides the address mapping function into two independent segments: a block mapping table for mapping logical block addresses to physical block addresses, and a page mapping table for mapping logical page addresses to physical page addresses within blocks. This segmentation allows each table to be optimized for its specific function, reducing the overall complexity of the FTL while maintaining full adaptability for both block-based and file-based applications
Solution Approach 2:
The patent creates a universal address mapping mechanism that can serve multiple functions simultaneously. The block mapping table and page mapping table work together to support both hard disk-like block operations and file system-like page operations, making the flash memory system universally applicable to different host interfaces and file systems without requiring separate translation layers for each application
2Productivity
If traditional block mapping and page mapping schemes are used in FTL, then sequential write operations are managed efficiently, but random write operations cannot be performed efficiently requiring erase-before-write operations
Solution Approach 1:
The patent introduces a dynamic mapping mechanism where the page mapping table can be updated independently of the block mapping table. When a random write operation is requested, the system dynamically allocates a new physical block address in the page mapping table without requiring erasure of the original block, enabling efficient random writes while maintaining sequential write performance through the block mapping table
Solution Approach 2:
By separating the block mapping function from the page mapping function into independent tables, the patent allows random write operations to be handled at the page level without affecting the block level structure. This segmentation enables the system to perform random writes by updating only the relevant page mapping entries, eliminating the need for erase-before-write operations that would otherwise be required in traditional unified mapping schemes
3Ease of manufacture
If flash memory uses erase-before-write operation characteristic, then the manufacturing simplicity is maintained, but the difficulty of detecting and measuring performance degrades due to the inability to perform random writes
Solution Approach 1:
The patent introduces an intermediary page mapping table that sits between the logical address space and the physical block structure. This intermediary layer translates random write requests into physical write operations that can be performed without erasure, maintaining the simple erase-before-write manufacturing characteristic of flash memory while enabling random write performance. The page mapping table acts as a mediator that hides the complexity of random write handling from the underlying flash memory structure
Solution Approach 2:
The system performs preliminary allocation of physical block addresses in the page mapping table before actual write operations. When a random write is requested, the corresponding page mapping entry is updated to point to a pre-allocated physical block, allowing the write to proceed immediately without erasure. This preliminary action separates the address translation function from the physical erase-write cycle, enabling performance measurement of random writes independent of the erase-before-write manufacturing constraint
Data Source
AI summary
Memory systems and mapping methods thereof are provided. In one embodiment of a memory system, an interface device is coupled between a flash memory and a host and stores a flash translation layer. The flash translation layer utilizes a data block mapping table and a page mapping table to manage data blocks and log blocks of the flash memory by a page mapping scheme and utilizes a random write page mapping table independent from the block mapping table and the page mapping table to manage the random write blocks by a random write mapping scheme. When a first predetermined condition is satisfied, the flash translation layer converts one of the data blocks (and one of the log block corresponding to the converted data block if any) into random write block(s) and utilizes the random write mapping schemes to manage the random write block(s). When a second predetermined condition is satisfied, the flash translation layer merges and converts random write block(s) into a data block and utilizes the page mapping scheme to manage the converted random write block(s).