Flash Translation Layer Table Rebuilding for Solid State Drives
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Solution Overview
Problem
Conventional solid state drives face issues with data loss and operational disruptions due to abnormal shutdowns, as the flash translation layer table (FTL) contents are not immediately stored in non-volatile memory, leading to the disappearance of critical mapping information during power interruptions.
Innovation Solution
A method for rebuilding the FTL table is implemented, where the controlling circuit identifies abnormal shutdowns using a power flag and sequentially updates the block programming serial numbers and auxiliary serial numbers to restore the correct mapping between physical allocation addresses and logical block addresses, ensuring data integrity and drive functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the FTL table is stored in the buffering circuit for quick access and updates, then the data access speed and update efficiency are improved, but the data reliability deteriorates because the FTL table contents are lost during abnormal shutdowns
Solution Approach 1:
The patent applies preliminary action by having the controlling circuit write back the FTL table contents to the non-volatile memory before an abnormal shutdown occurs. The power flag mechanism triggers this write-back operation in advance, ensuring that the critical mapping information is preserved in the non-volatile memory even when the buffering circuit loses power, thus resolving the contradiction between fast access and data reliability
Solution Approach 2:
The patent uses copying by maintaining duplicate copies of the FTL table in both the buffering circuit (for quick access) and the non-volatile memory (for reliability). The controlling circuit synchronizes these copies by writing back changes to the non-volatile memory, ensuring that both locations have consistent data while each location serves its specific function optimally
2Reliability
If the FTL table is written back to non-volatile memory before shutdown, then the data reliability is improved, but the operational disruptions increase due to the additional write-back operation required during abnormal shutdowns
Solution Approach 1:
The patent applies feedback by using the power flag as a signal to trigger the write-back operation. When an abnormal shutdown is detected through the power flag, the controlling circuit receives feedback and immediately executes the write-back of the FTL table to the non-volatile memory, then restores normal operation. This feedback mechanism ensures reliability while minimizing operational disruption by acting quickly upon detection
3Manufacturing precision
If the controlling circuit sequentially updates block programming serial numbers and auxiliary serial numbers to rebuild the FTL table, then the data integrity is improved, but the time consumption increases during the rebuilding process
Solution Approach 1:
The patent applies preliminary action by pre-establishing the block programming serial numbers and auxiliary serial numbers in the non-volatile memory before an abnormal shutdown. When rebuilding is needed, the controlling circuit only needs to read these pre-existing serial number sequences rather than reconstructing everything from scratch, significantly reducing the rebuilding time while maintaining data integrity through the systematic sequential update process
Solution Approach 2:
The patent uses copying by replicating the serial number information (block programming serial numbers and auxiliary serial numbers) in both the buffering circuit and non-volatile memory. During rebuilding, the controlling circuit copies and utilizes these pre-stored serial number sequences to efficiently reconstruct the FTL table mapping relationships, reducing the time required compared to creating mappings from scratch
Data Source
AI summary
A flash translation layer table rebuilding method for a solid state drive is provided. The solid state drive includes a non-volatile memory and a buffering circuit. Firstly, a flash translation layer table is loaded from the non-volatile memory to the buffering circuit. In case that an abnormal shutdown event occurs, plural blocks of the non-volatile memory to be read are determined according to a specified block programming serial number of the flash translation layer table. Then, a read sequence of reading the plural blocks is determined according to a block programming serial number or an auxiliary serial number corresponding to the block. The contents of the blocks are read according to the read sequence. A mapping relationship between plural physical allocation addresses and plural logical block addresses of the flash translation layer table is updated.