Flash Translation Layer Wear-Leveling for SSD Endurance

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Solution Overview

Problem

Current operating systems and file systems are not optimized to take advantage of the capabilities of solid state drives (SSDs), particularly NAND flash-based storage devices, which require different data management strategies due to their parallel access nature and limited data retention, leading to inefficiencies in data storage and retrieval.

Innovation Solution

A log-structured file system with a flash translation layer that uses append-only policies, over-provisioning, and dynamic block management to optimize data storage on SSDs, allowing for efficient use of multiple channels and maintaining data integrity through monitoring and managing program/erase cycles, enabling efficient data distribution and wear-leveling across blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional file systems are used with SSDs, then compatibility with existing operating systems is maintained, but storage performance and efficiency are not optimized

Engineering Contradiction:
Improvestorage performanceVSAvoidfile system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a flash translation layer as an intermediary between the traditional file system and the SSD. This translation layer converts traditional file system operations into SSD-optimized operations, allowing the system to maintain compatibility with existing operating systems while achieving optimized storage performance through append-only policies and dynamic block management specific to SSD characteristics

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the file system into two distinct components: the traditional file system layer that maintains compatibility, and the flash translation layer that provides SSD optimization. This segmentation allows each layer to operate independently with its own optimization strategies, resolving the contradiction between maintaining simplicity and achieving high performance

Inventive Principle:
Principle #1Segmentation

2Speed

If direct overwriting of existing data is performed, then data update speed is improved, but data integrity and reliability deteriorate due to limited programming cycles in NAND flash memory

Engineering Contradiction:
Improvedata update speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements a preliminary action by allocating new blocks in advance for data updates. Instead of directly overwriting existing data, the system pre-allocates fresh blocks, copies data to these new blocks, and then atomically switches pointers to the new location. This preliminary preparation enables fast updates while preserving data integrity by avoiding partial writes to the same block

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs a discard and recover mechanism where old blocks containing overwritten data are marked as invalid and eventually discarded through garbage collection, while new blocks are recovered and allocated for future writes. This approach maintains data integrity by ensuring each write operation targets a fresh block with full programming cycles available, while still achieving update speed through efficient block management

Inventive Principle:
Principle #34Discarding and recovering

3Speed

If data are concentrated in fewer blocks, then access speed is improved, but wear on specific blocks increases reducing overall device lifespan

Engineering Contradiction:
Improveaccess speedVSAvoiddevice lifespan
Core Design Contradiction:
SpeedVSDuration of action of stationary object

Solution Approach 1:

The patent implements dynamic block management where the mapping between logical addresses and physical blocks is not static but continuously adapts based on wear levels and access patterns. The flash translation layer dynamically selects target blocks for writes, considering factors like current wear distribution and performance requirements, thereby balancing access speed with device lifespan through flexible, adaptive block allocation

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of block selection from a fixed or simple round-robin approach to a wear-aware dynamic selection process. The system monitors programming cycle counts for each block and adjusts block allocation decisions based on these parameters, selecting blocks with lower wear for new writes. This parameter change enables the system to distribute wear more evenly across all blocks while maintaining efficient access performance

Inventive Principle:
Principle #35Parameter changes

4Productivity

If multiple parallel channels are utilized, then data throughput is improved, but data distribution complexity and management overhead increase

Engineering Contradiction:
Improvedata throughputVSAvoiddata distribution complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the complexity of multi-channel data distribution management into the flash translation layer, which presents a simplified interface to the traditional file system. The translation layer handles the complexity of distributing data across multiple parallel channels, managing channel allocation, and coordinating writes, while the upper layers continue to operate with simple sequential write operations. This merging of complexity into a dedicated translation layer enables high throughput without increasing overall system complexity

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9342260B2Methods for writing data to non-volatile memory-based mass storage devices
Publication Date: 2016.05.17 KIOXIA CORP
  • US9342260B2 patent drawing
  • US9342260B2 patent drawing
  • US9342260B2 patent drawing

AI summary

Methods of operating a non-volatile solid state memory-based mass storage device having at least one non-volatile memory component. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.