Unified Paging Scheme for Flash Translation Tables

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Solution Overview

Problem

Flash storage systems face challenges in efficiently managing large translation tables due to limited memory capacity, requiring quick and reliable access while minimizing memory consumption, especially when dealing with dense and sparse translation tables.

Innovation Solution

A unified paging method that dynamically stores and retrieves translation structures, using a hash function to identify dump units and determine dump groups, and employing a linked list to manage translation table entries, allowing for efficient storage and retrieval without incurring high latency costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the entire translation table is stored in memory (DRAM), then access speed is improved, but memory consumption increases significantly

Engineering Contradiction:
Improvetranslation table access speedVSAvoidmemory consumption
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The translation table is divided into multiple pages, with only the currently needed page loaded into DRAM. This segmentation allows the system to maintain fast access speeds for the active page while significantly reducing overall memory consumption by storing the majority of the translation table in non-volatile memory.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical storage architecture that adds a new dimension to translation table storage. Instead of a single flat memory structure, it creates a two-level system with DRAM for active pages and non-volatile memory for inactive pages, enabling the system to scale translation table size without proportionally increasing DRAM usage.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If translation table entries are stored sparsely with explicit logical block numbers, then address range flexibility is improved, but lookup complexity increases

Engineering Contradiction:
Improveaddress range flexibilityVSAvoidlookup complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal translation table structure that handles both dense and sparse address ranges using the same page-based mechanism. The hash function and page structure work uniformly regardless of whether the address space is densely or sparsely populated, eliminating the need for different data structures while maintaining flexibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent replaces complex match-based lookup mechanisms with a simpler hash-based page indexing system. Instead of searching through sparse entries with explicit logical block numbers, the system uses hash functions to directly compute page locations, significantly reducing lookup complexity while preserving address range flexibility.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Quantity of substance

If the translation table is stored in non-volatile memory, then memory capacity is improved, but access latency increases

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-loading the required translation table page into DRAM before it is actually needed for translation operations. The controller anticipates page access needs and proactively loads pages from non-volatile memory to the DRAM cache, ensuring that when translation operations occur, the data is already in fast memory, thus minimizing access latency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10725903B2Unified paging scheme for dense and sparse translation tables on flash storage systems
Publication Date: 2020.07.28 SANDISK TECHNOLOGIES LLC
  • US10725903B2 patent drawing
  • US10725903B2 patent drawing
  • US10725903B2 patent drawing

AI summary

A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive a read request for a first translation table entry associated with a logical block, identify a dump unit associated with the logical block using a hash function, determine a dump group associated with the dump unit, and identify a second translation table entry associated with the dump unit.