Flash Memory Trim Data Read via Sense Amplifier Bypass
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Solution Overview
Problem
Flash memory devices face challenges in reliably reading out trim data during power-up due to variations in internal reference voltage or current, which are critical for adjusting analog levels and ensuring proper operation, especially when the normal read operation relies on untrimmed reference current values.
Innovation Solution
A trim data read out method and circuit that supports a two-way read operation, allowing at least some trim data to be read out upon powering up through a bypass read-out path that bypasses the sense amplifier, enabling the adjustment of critical circuit elements like the reference current before proceeding with the normal read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the normal read operation is used to read out trim data, then the read operation can proceed through the standard sense amplifier path, but the readout may fail because the reference current has not been trimmed yet and is unstable
Solution Approach 1:
The patent segments the readout path into two distinct paths: a normal read path through the sense amplifier for regular data reads, and a bypass path for trim data reads. This segmentation allows trim data to be read out independently without relying on the untrimmed reference current that would cause failures in the normal path.
Solution Approach 2:
The patent introduces a bypass path as an intermediary mechanism that mediates between the trim data storage and the output register. This bypass path includes a bypass readout transistor that provides an alternative route for reading trim data without passing through the sense amplifier and without requiring trimmed reference current.
2Ease of manufacture
If the sense amplifier path is used for trim data readout, then the existing read circuitry can be utilized, but the operation fails due to untrimmed reference current variations
Solution Approach 1:
The patent implements preliminary action by providing a dedicated bypass path that is specifically designed and prepared for reading trim data before the reference current trimming is completed. This bypass path is activated during power-up or reset conditions to ensure trim data can be read out successfully before the normal read path becomes reliable.
Solution Approach 2:
The patent introduces dynamic control through a bypass enable signal that switches between the normal read path and the bypass path. The bypass readout transistor is dynamically controlled to be conductive during power-up/reset conditions and non-conductive during normal operation, allowing the system to adapt its readout path based on operational state.
Data Source
AI summary
A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured to receive the first signal. The trim data latch circuit is configured to store a signal related to the first signal as a trim data value and to provide trim data value to circuitry of the non-volatile memory device. The trim data value may be applied to adjust a signal level of the circuitry of the non-volatile memory device.