Flash Memory Verification Counting for Early Program Pass/Fail
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Solution Overview
Problem
The time-consuming failure bit counting operation in the verification step of flash memory devices delays the execution of subsequent program loops, reducing the overall program speed.
Innovation Solution
A nonvolatile memory device with a page buffer circuit and a pass/fail checker that divides the verification read result into stages, sequentially performs failure bit counting, and adjusts reference values based on the stage progress, allowing for early determination of program pass or failure, thereby skipping unnecessary counting operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the failure bit counting operation is performed completely for all verification read results, then the accuracy of program pass/fail determination is improved, but the program speed deteriorates
Solution Approach 1:
The patent applies preliminary action by performing failure bit counting operation in stages and determining program pass/fail status before completing all counting operations. The P/F checker sequentially counts failure bits and compares with reference value at intermediate points, allowing early termination when the outcome is already determined, thus avoiding unnecessary complete counting operations
Solution Approach 2:
The patent segments the failure bit counting operation into multiple stages rather than performing it as a single complete operation. The verification read result is divided into stages, and the P/F checker performs counting and comparison operations at each stage, enabling early determination of program pass/fail status and skipping remaining counting operations when the result is already known
2Reliability
If the failure bit counting operation is performed completely, then the reliability of verification is improved, but the time consumption increases
Solution Approach 1:
The patent performs preliminary determination of program pass/fail status during the counting process by comparing accumulated failure bit counts with reference values at intermediate stages. When the comparison result already determines the final outcome, the remaining counting operations are skipped, reducing time loss while maintaining verification reliability
Solution Approach 2:
The patent applies partial action by performing only the necessary portion of the failure bit counting operation required to determine program pass/fail status. Instead of always completing the full counting operation, the system performs counting partially and terminates early when the result is determined, reducing time consumption while maintaining sufficient verification reliability
Data Source
AI summary
A memory device including a first substrate, a peripheral circuit provided on the first substrate, a first metal bonding layer provided on the peripheral circuit, a second metal bonding layer directly bonded to the first metal bonding layer, a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.