Flash Memory Readout Using Viterbi Decoding for ISI Errors
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Solution Overview
Problem
As the geometry of flash memory devices is reduced, inter-signal interference (ISI) between neighboring memory cells affects the operation, particularly the data read operation, necessitating an error-correcting logic or algorithm to ensure accurate data retrieval.
Innovation Solution
Implementing a Viterbi algorithm or its variant to process raw data from flash memory devices, constructing a trellis graph with all possible data states, and determining a data path with minimum error to provide correct data, thereby correcting data read operations affected by inter-signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the geometry of flash memory is reduced to increase storage density, then storage capacity is improved, but inter-signal interference between neighboring memory cells increases
Solution Approach 1:
The patent segments the data reading process into multiple voltage levels (e.g., first read voltage, second read voltage, third read voltage) applied to different word lines. This segmentation allows the system to read data from multiple memory cells simultaneously at different voltage levels, then combine the results to correct inter-signal interference errors, thereby maintaining high storage density while mitigating interference effects.
2Measurement precision
If error-correcting logic is added to correct inter-signal interference, then data accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where data is read at multiple voltage levels, and the results are combined to generate corrected data. The system uses the read results from different voltage levels as feedback to identify and correct errors caused by inter-signal interference, thereby improving data accuracy without requiring complex external error correction codes.
3Reliability
If multiple read voltages are applied to correct errors, then data reliability is improved, but read operation time increases
Solution Approach 1:
The patent employs periodic action by applying read voltages in discrete stages (first read voltage, second read voltage, third read voltage) rather than continuously. Each voltage level is applied for a specific duration to read data from specific word lines, and the results are combined. This periodic approach ensures data reliability while minimizing the total read time compared to exhaustive error correction methods.
Data Source
AI summary
Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can decode error correction codes (ECC).