Flash Memory Voltage Generator Switched Capacitor Speed Power Trade-off
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Solution Overview
Problem
Conventional voltage generators in flash memory systems face challenges in generating comparison voltages quickly while minimizing power consumption, as reducing resistance to speed up voltage generation increases power consumption, affecting the efficiency of read operations.
Innovation Solution
The voltage generator incorporates a switched capacitor circuit that discharges electric current along a first path when the read command is disabled and transitions to a second path connected to a switched capacitor circuit when enabled, using a switching pulse signal to distribute electric charges and adjust the comparison voltage more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If resistance is reduced to speed up voltage generation, then voltage generation speed is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic switching of the switching element (transistor) to control the capacitor's charging and discharging cycles. By periodically connecting and disconnecting the capacitor to different voltage nodes based on read command states, the system achieves rapid voltage transitions without requiring continuously low resistance, thus maintaining speed while controlling power consumption.
Solution Approach 2:
The patent dynamically changes the circuit configuration by switching the transistor between on and off states. When the read command is enabled, the transistor connects the capacitor to generate the comparison voltage quickly; when disabled, it disconnects to reduce power consumption. This dynamic reconfiguration allows the system to adapt its resistance characteristics based on operational requirements.
2Speed
If the voltage generator operates continuously to maintain readiness, then voltage generation speed is improved, but power consumption increases
Solution Approach 1:
The patent pre-charges the capacitor to a specific voltage level (VCC) when the read command is disabled, preparing it for rapid comparison voltage generation when needed. This preliminary action ensures that when a read operation is initiated, the voltage generator can quickly produce the required comparison voltage without delay, while the capacitor maintains this prepared state efficiently.
Solution Approach 2:
The patent discards the pre-charged state of the capacitor when the read command is disabled to minimize power consumption, and recovers this pre-charged state when the read command is enabled to ensure fast voltage generation. The switching element controls when the capacitor holds charge (during read operations) and when it is discharged (during idle periods), optimizing the balance between speed and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for faster generation and discharge of comparison voltages, reducing the time required to charge and discharge, thereby enhancing the speed of voltage generation without significantly increasing power consumption.
Implementation Method 1
a second terminal of the fourth N-type MOS transistor N4 may be connected to a second power supply voltage VSS. A first terminal of a capacitor C may be connected to a common node between the sixth P-type MOS transistor P6 and the fourth N-type MOS transistor N4, and a second terminal of the capacitor C may be connected to the second power supply voltage VSS
Data Source
AI summary
A voltage generator and methods thereof are provided. The example voltage generator may include a voltage comparison block which generates an output voltage in response to a read command, the output voltage corresponding to a difference between a reference voltage and a determination voltage and a voltage generation block which outputs the determination voltage and a comparison voltage in response to the read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and the output voltage. A first example method may include outputting a determination voltage and a comparison voltage in response to a read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and an output voltage, the output voltage generated in response to the read command and corresponding to a difference between the reference voltage and the determination voltage. A second example method may include maintaining a comparison voltage at a first voltage level if a read command is disabled and transitioning the comparison voltage to a second voltage level if the read command is enabled by discharging electric current along a first path, the first path connected to a first node coupled to at least one resistor, and a second path, the second path connected to a second node coupled with a switched capacitor circuit, the switched capacitor circuit including a capacitor which is selectively connected to the second node in response to the enabled read command.