Flash Memory Wear Leveling via DRAM Buffer and ASIC Control
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Solution Overview
Problem
Conventional DRAM technology is not directly substitutable with FLASH memory due to bandwidth issues, limiting the use of FLASH memory in applications that require high-speed data access.
Innovation Solution
Implementing a system with an application-specific integrated circuit (ASIC) to control timing and a DRAM buffer for high-speed write operations, combined with wear leveling mechanisms and operating system enhancements to manage memory wear and optimize FLASH memory usage, allowing partial allocation of data from FLASH to DRAM for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If FLASH memory is used to replace DRAM, then density and cost are improved, but bandwidth and access speed deteriorate
Solution Approach 1:
The memory system is segmented into multiple FLASH memory devices arranged in a bank array, with each device containing multiple blocks and pages. This segmentation allows parallel access to different memory regions, effectively increasing the overall bandwidth while maintaining high density.
Solution Approach 2:
A memory controller acts as an intermediary between the host system and the FLASH memory devices. It manages data transfer operations, handles wear leveling, and coordinates access to multiple FLASH devices, thereby overcoming the inherent bandwidth limitations of individual FLASH devices through intelligent data routing and parallel operation management.
2Quantity of substance
If continuous write operations are performed in FLASH memory, then data storage capacity is improved, but memory sector lifespan deteriorates due to wear
Solution Approach 1:
The memory controller performs preliminary wear leveling by proactively redistributing write operations across different blocks and pages before any single sector becomes excessively worn. It maintains a mapping structure that tracks the wear status of each block and pre-emptively remaps data to less-worn blocks, preventing any single sector from reaching its write endurance limit.
Solution Approach 2:
The system dynamically changes the physical location parameters of stored data by remapping logical block addresses to different physical block addresses based on wear status. This parameter transformation allows the same logical data to be stored in different physical locations, distributing wear evenly across all FLASH memory sectors and extending overall memory lifespan.
3Reliability
If wear leveling mechanisms are implemented, then memory sector lifespan is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed as a multi-functional device that simultaneously performs wear leveling, bad block management, data encryption, error correction, and address translation. By consolidating these functions into a single controller unit, the patent reduces overall system complexity compared to having separate dedicated circuits for each function, while still providing comprehensive wear leveling protection.
Data Source
AI summary
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.