Flash Memory Wear Leveling Using Segment Write Counters
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Solution Overview
Problem
Existing flash memory controllers face processing overhead issues when handling sequential data streams due to the use of translation tables for wear leveling, leading to reduced performance and the inability to handle incoming data in real-time, especially in applications like black box recorders that require continuous data recording.
Innovation Solution
Implementing a write counter mechanism that selects recording segments based on data write counters to distribute program/erase cycles evenly, eliminating the need for a translation table and allowing direct writing to physical blocks, thereby reducing processing overhead and improving sustained write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If translation tables are used for wear leveling, then data can be stored in non-volatile memory, but processing overhead increases and real-time data handling capability deteriorates
Solution Approach 1:
The patent extracts and eliminates the translation table component from the memory controller. Instead of using a translation table to map logical addresses to physical addresses for wear leveling, the invention directly writes data to physical memory locations using simplified address calculation, thereby removing the processing bottleneck while maintaining wear leveling functionality through alternating buffer regions.
Solution Approach 2:
The patent divides the non-volatile memory into multiple alternating buffer regions (first buffer region, second buffer region, third buffer region, etc.) that can be sequentially activated. This segmentation allows the system to switch between regions without complex translation operations, enabling real-time data handling while distributing write operations across multiple regions to achieve wear leveling.
2Reliability
If translation tables are used for wear leveling, then data distribution across memory blocks is improved, but controller complexity and processing overhead increase
Solution Approach 1:
The invention removes the translation table structure entirely from the controller architecture. Wear leveling is achieved through a simpler mechanism that alternates between predefined buffer regions using direct address calculation, eliminating the need for complex translation operations and reducing controller complexity while maintaining effective wear leveling.
Solution Approach 2:
Instead of using a translation table to indirectly map logical addresses to physical addresses (the conventional approach), the patent inverts the approach by directly calculating physical addresses through alternating buffer region selection. This inversion simplifies the controller logic while achieving the same wear leveling objective.
3Reliability
If translation tables are used for wear leveling, then data can be stored with even distribution, but sustained write performance deteriorates
Solution Approach 1:
The patent segments the non-volatile memory into alternating buffer regions that can be sequentially written to. This segmentation enables sustained write performance by allowing the system to switch between regions without complex translation operations, while still achieving uniform data distribution and wear leveling across all regions over time.
Solution Approach 2:
The patent implements periodic switching between alternating buffer regions for data writing. This periodic action between first, second, third, and subsequent buffer regions enables high-speed sustained writes by avoiding translation table lookups, while ensuring uniform wear distribution across all regions through systematic alternation.
Data Source
AI summary
A memory system has a controller (e.g., CPU, FPGA, or GPU) and recording segments in a non-volatile memory (e.g., a flash memory device) used by the controller to store data. The controller is configured to: maintain data write counters for the recording segments; select a first segment of the recording segments for recording data from a host system, wherein selecting the first segment comprises scanning the data write counters to identify a first data write counter corresponding to the first segment; receive, from the host system, data to be recorded by the non-volatile memory; and write the received data to the selected first segment.