Flash Memory Wear Leveling for Direct-Mapped Access

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Solution Overview

Problem

Current wear leveling techniques for nonvolatile memory devices, such as flash memory, are not applicable to direct memory access devices and can impact performance due to complex algorithms, leading to premature failure of memory cells from repetitive erasures and rewrites.

Innovation Solution

Implementing a platform-based wear leveling system that includes a receiver and a wear leveling module to determine physical locations for logical write requests, using a low-level driver module, error correction code, queue management, and flash translation layer to distribute write operations and extend the life of nonvolatile memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wear leveling mechanisms are applied at the flash translation layer, then data erasures and re-writes are distributed over the entire memory device, but the mechanisms are not applicable to direct memory access devices and low-level driver accesses

Engineering Contradiction:
Improvememory cell life spanVSAvoidapplicability to direct memory access devices
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The wear leveling module is designed to handle multiple types of access methods universally. It processes both high-level flash translation layer requests and low-level direct memory access requests through a unified interface, making the wear leveling mechanism applicable to various access methodologies without requiring separate implementations for each type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The wear leveling module acts as an intermediary between the memory controller and the flash memory device. It intercepts write requests before they reach the physical memory, applies wear leveling algorithms, and manages the actual write operations, thereby enabling wear leveling for direct memory access devices without modifying the memory hardware itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If complex wear leveling algorithms are employed to distribute write operations, then memory cell wear is evenly distributed, but performance is significantly impacted and delays become more pronounced as flash memory size increases

Engineering Contradiction:
Improvememory cell life spanVSAvoidmemory access performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by pre-calculating wear leveling strategies and preparing write operations in advance. It maintains a queue of write requests and pre-computes the optimal distribution pattern, allowing the actual memory writes to be executed more efficiently without runtime algorithm complexity impacting performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The wear leveling mechanism dynamically adjusts its behavior based on the current state of the flash memory device. It monitors write patterns, adapts the distribution strategy in real-time, and modifies its operation based on memory availability and access patterns, thereby optimizing between wear distribution and performance requirements.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7917689B2Methods and apparatuses for nonvolatile memory wear leveling
Publication Date: 2011.03.29 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US7917689B2 patent drawing
  • US7917689B2 patent drawing
  • US7917689B2 patent drawing

AI summary

Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments an apparatus that has a receiver and a wear leveling module. The receiver may receive low-level write requests to update direct-mapped values of nonvolatile memory. The wear leveling module may determine physical locations of the nonvolatile memory that correspond to logical locations of the write requests. Alternative embodiments may comprise systems or apparatuses that include one or more various types of additional modules, such as low-level driver modules, error correction code modules, queue modules, bad block management modules, and flash translation layer modules. Other embodiments comprise computer program products that receive a direct-mapped low-level write request, determine a physical write location of nonvolatile memory that corresponds to a logical write location of the low-level write request.