Flash Memory Wear Leveling via Index Array Management
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Solution Overview
Problem
Flash memory systems that emulate EEPROM devices face issues with uneven wear and 'program disturb' due to repeated programming and erase operations, leading to device unavailability and unintended programming of adjacent cells.
Innovation Solution
Implementing a wear leveling system that uses an index array to manage bit-level programming, allowing for skipping, reprogramming, or shifting of data within the flash memory cells to distribute wear evenly and prevent program disturb, while enabling bit-level programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If repeated programming and erase operations are performed in flash memory cells, then data storage functionality is maintained, but uneven wear occurs leading to device degradation
Solution Approach 1:
The patent segments the flash memory into multiple physical blocks (first block, second block, third block) and implements wear leveling by distributing programming and erase operations across these blocks. When a block reaches its wear threshold, the system transitions to another block, thereby segmenting the wear burden and extending overall device endurance while maintaining reliability.
2Productivity
If repeated programming operations are performed on the same flash memory cells, then data can be updated, but program disturb phenomena occur causing unintended programming of adjacent cells
Solution Approach 1:
The patent divides the flash memory into multiple physical blocks and assigns different data sets to different blocks. By segmenting the storage space and managing data distribution across blocks, the system reduces the frequency of repeated programming operations on the same cells, thereby minimizing program disturb effects on adjacent cells while maintaining data update capability.
Solution Approach 2:
The patent introduces a controller that acts as an intermediary between the host system and the flash memory blocks. This controller manages the wear leveling algorithm, monitors block wear status, and intelligently directs programming operations to appropriate blocks, thereby mediating between data update requirements and program disturb prevention.
3Duration of action of stationary object
If wear leveling is implemented to distribute wear evenly, then device endurance is extended, but system complexity increases due to additional management mechanisms
Solution Approach 1:
The patent segments the flash memory into a fixed number of physical blocks (first, second, third blocks) with predetermined capacities. This segmentation simplifies wear leveling management by providing clear boundaries and structured organization, making it easier to track and manage wear distribution compared to more complex dynamic partitioning schemes.
Solution Approach 2:
The patent implements wear leveling by changing the operational parameters of different blocks over time. Specifically, it monitors the number of programming and erase operations on each block and dynamically adjusts which block is active for data storage based on wear thresholds. This parameter-based management approach extends device endurance while keeping the control mechanism relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively distributes wear across all portions of the flash memory, preventing device degradation and reducing program disturb phenomena, allowing for extended device endurance and accurate data storage.
Implementation Method 1
The non-volatile memory cell is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line terminal and zero volts to the bit line terminal and source line terminal
Implementation Method 2
The cell is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the source line, a small voltage on the word line terminal, and a programming current on the bit line terminal
Data Source
AI summary
The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.