Flash Memory Wear-Leveling via Minimal Erase Count Tracking

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Solution Overview

Problem

The static wear-leveling algorithm in flash memory devices is inefficient, leading to uneven erase count distribution across physical blocks, causing some blocks to be prematurely damaged while others are underutilized, due to frequent data migration and poor selection strategies, which reduces the lifetime of flash memory.

Innovation Solution

A data retention method that maintains a minimum erase count and number for blocks in a flash memory array, where the controller manages erase operations to balance erase counts by scanning only when necessary, storing these values to prevent loss during power outages, and selectively migrates data based on erase count thresholds to optimize wear-leveling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If static wear-leveling algorithm is implemented to balance erase counts, then flash memory lifetime is improved, but hardware overhead increases due to frequent scanning

Engineering Contradiction:
Improveflash memory lifetimeVSAvoidhardware overhead
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The controller pre-calculates and stores the minimum erase count and minimum erase number before power-off. This preliminary action allows the wear-leveling algorithm to resume efficiently after power restoration without requiring extensive scanning, thus extending flash memory lifetime while reducing hardware overhead.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and stores only the critical parameters (minimum erase count and minimum erase number) from the flash memory array, rather than scanning the entire array. This extraction approach maintains wear-leveling effectiveness while significantly reducing the scanning overhead and hardware complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If minimum erase count and number are stored in flash memory array, then data retention during power loss is improved, but storage space is consumed

Engineering Contradiction:
Improvedata retention during power lossVSAvoidstorage space
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent stores the minimum erase count and minimum erase number in a specific localized region of the flash memory array rather than distributing storage requirements across the entire array. This localized storage approach ensures data retention during power loss while consuming minimal storage space.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If frequent scanning is performed to maintain wear-leveling, then erase count distribution is optimized, but processing time increases

Engineering Contradiction:
Improveerase count distribution uniformityVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent implements periodic wear-leveling operations triggered by power events rather than continuous scanning. The controller performs wear-leveling maintenance at periodic intervals based on power cycles, using the stored minimum erase count and number to guide operations. This periodic approach maintains erase count distribution uniformity while minimizing processing time loss.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11249894B2Storage devices and data retention methods thereof
Publication Date: 2022.02.15 VIA TECH INC
  • US11249894B2 patent drawing
  • US11249894B2 patent drawing
  • US11249894B2 patent drawing

AI summary

A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. A minimal erase number of blocks have a minimal erase count in the plurality of blocks. When one of the minimal erase number of blocks is erased, the controller subtracts 1 from the minimal erase number.