Flash Memory Word Line Decoder Low Voltage Power Reduction
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Solution Overview
Problem
Conventional word line decoders in flash memory devices experience increased power consumption due to the formation of improper current paths when the supply voltage falls below 1.8V, leading to inefficiencies in operations such as programming, erasing, and reading.
Innovation Solution
A word line decoder design that includes specific transistor configurations, such as NMOS and PMOS transistors, to prevent the formation of DC current paths from high voltage to ground voltage, ensuring that the supply voltage maintains the necessary voltage levels for proper operation even at reduced voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional word line decoder circuits are used, then the device can operate at low supply voltages, but improper current paths form causing increased power consumption
Solution Approach 1:
The patent introduces intermediate control transistors (third transistor with gate connected to block word line driving signal line, fourth transistor with gate connected to string selection voltage line) that act as mediators to prevent direct current paths between high voltage and ground. These intermediary elements control the flow of current through the decoder circuit, ensuring that no improper DC paths form even when supply voltage drops below 1.8V, thus reducing power consumption while maintaining operation reliability
Solution Approach 2:
The patent changes the voltage control parameters by connecting transistor gates to different voltage lines (block word line driving signal line, string selection voltage line, ground selection voltage line) instead of using conventional fixed biasing. This parameter change ensures that transistors remain properly controlled across a wide voltage range, preventing the formation of current paths that would cause excessive power consumption at low supply voltages
Data Source
AI summary
Provided is a word line decoder suitable to a low operating voltage of a flash memory device. The word line decoder generates a block word line driving signal of a high voltage in response to a block selection signal. The word line decoder includes a first inverter receiving the block selection signal, a second inverter receiving an output of the first inverter, and first and second serially connected transistors receiving an output of the second inverter and outputting the block word line driving signal. The gates of the first and second transistors are connected to a supply voltage terminal. The word line decoder includes a third transistor having a source connected to a high voltage terminal and a gate connected to a line transmitting the block word line driving signal, a fourth transistor connected between the drain of the third transistor and the block word line driving signal line, a fifth transistor connected between the drain of the third transistor and the gate of the fourth transistor and having a gate connected to the block word line driving signal line, and a sixth transistor connected between the output of the first inverter and the gate of the second transistor and having a gate connected to the supply voltage terminal.