Flash Memory Word Line Width Control via Self-Aligned Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current flash memory fabrication methods using photoresist to define word lines result in inconsistent line widths due to lithographic tool offsets, leading to manufacturing inefficiencies.
Innovation Solution
A self-aligned process is employed to form word lines, utilizing a conductive layer with specific profiles and a sacrificial layer to control the etching process, ensuring consistent widths through anisotropic etching, eliminating the need for photoresist and allowing for adjustable word line widths with a thinner conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photoresist is used to define word lines, then the fabrication process is simple, but the word line width becomes inconsistent due to lithographic tool offset
Solution Approach 1:
The patent employs a self-aligned process where the word line pattern is automatically defined by the relative positioning of etching steps rather than by photoresist alignment. The conductive layer is etched to form word lines that are inherently aligned with the gate structures through the self-aligned nature of the process, eliminating the need for photoresist-based alignment and thus achieving consistent word line widths without sacrificing fabrication simplicity
Solution Approach 2:
The patent performs preliminary formation of the conductive layer with a specific mountain profile before the final word line definition step. This preliminary structure serves as a template that guides the subsequent self-aligned etching process, ensuring that the word lines are formed with consistent widths and proper alignment to the gate structures before the actual pattern definition occurs
2Adaptability or versatility
If photoresist is used to define word lines, then the process is conventional, but the word line width cannot be precisely controlled
Solution Approach 1:
The patent utilizes parameter changes in the etching process to achieve precise word line width control. By adjusting etching parameters such as etch rate, etch time, and anisotropy, the process can precisely define the word line width. The self-aligned nature of the etching process ensures that these parameter changes directly translate to controlled word line dimensions without being affected by photoresist alignment variations
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element in the self-aligned process. This sacrificial layer is formed conformally on the conductive layer and serves as a mediator that defines the word line pattern through selective removal. The sacrificial layer acts as a template that translates the desired word line width into a physical structure that guides the final etching step, enabling precise width control independent of photoresist limitations
3Length of moving object
If a thicker conductive layer is used to achieve wider word lines, then the word line width increases, but the fabrication complexity increases
Solution Approach 1:
The patent transitions from controlling word line width through horizontal photoresist patterning to controlling it through vertical conductive layer thickness and sacrificial layer thickness. By moving the control dimension from the lateral plane to the vertical plane, the process achieves wider word lines through thicker conductive layers while maintaining fabrication simplicity through the self-aligned etching approach that automatically translates vertical dimensions to horizontal features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent word line widths, reduces fabrication costs, and improves manufacturing precision by eliminating the need for photoresist and allowing for wider word lines with thinner conductive layers, enhancing the overall efficiency of the flash memory production process.
Implementation Method 1
a first anisotropic etching process is performed to remove the sacrificial layer on the summit of the first mountain profile, on the summit of the second mountain profile, on the first flat profile and on the second flat profile
Data Source
AI summary
A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The sharp angle connects to the first concave surface.