Flash Write Mapping for Soft-Decision Decoding Hard Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory technologies face significant challenges with single write errors, particularly at good signal-to-noise ratios, which affect soft-decision decoding success and result in hard errors due to cells being stuck in certain states or mis-programmed, leading to performance degradation and saturated log-likelihood ratio values.
Innovation Solution
A write mapping technique is introduced to mitigate hard errors by creating dependencies between data bits, storing mapped bits in multiple memory cells, and modifying soft-decision information through intentional inter-cell interference, increasing Euclidean space distances between likely sequences and avoiding saturated log-likelihood ratio values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If soft-decision decoding is used in flash memory, then decoding accuracy is improved, but write errors from stuck cells and mis-programming cause saturated log-likelihood ratio values that degrade performance
Solution Approach 1:
The patent applies preliminary action by performing write mapping before data is written to memory. The mapping process creates dependencies between data bits and selects write patterns that avoid known error-prone states in advance. This prevents stuck cell and mis-programming issues from causing saturated log-likelihood ratio values during soft-decision decoding, thereby maintaining both decoding accuracy and performance stability.
2Reliability
If write mapping with inter-cell dependencies is implemented, then hard error mitigation is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the write mapping process into distinct functional modules: dependency creation between bits, pattern selection based on memory state, and selective application to different memory regions. This modular segmentation reduces implementation complexity while maintaining effective hard error mitigation through inter-cell dependencies.
Solution Approach 2:
The patent introduces an intermediary mapping layer between the data to be stored and the physical memory cells. This mapping intermediary creates controlled dependencies between bits and selects write patterns that mitigate hard errors without requiring complex changes to the underlying memory structure, thereby reducing overall device complexity.
3Reliability
If multiple memory cells are used to store mapped bits, then redundancy and error protection are improved, but memory capacity utilization decreases
Solution Approach 1:
The patent applies partial action by selectively applying write mapping and multi-cell storage only to specific data bits and memory regions where error protection is most beneficial. Not all bits require the same level of protection, allowing the system to achieve adequate error protection while minimizing the impact on overall storage capacity utilization.
Data Source
AI summary
An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.