Flash Memory RAID-Like Parity Placement for Better Space Use

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Solution Overview

Problem

Conventional flash memory systems have a low utilization rate of memory space due to the need to dedicate a significant portion for parity check codes, reducing the effective storage capacity for user data.

Innovation Solution

Implementing a RAID-like error correction code encoding operation in a flash memory apparatus, which classifies data into groups and uses XOR encoding to generate parity check codes, allowing these codes to be efficiently stored and used for error correction across multiple-level-cell blocks, thereby reducing the need for excessive parity check code storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional parity check coding is used to ensure error correction capability, then data reliability is improved, but memory space utilization deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoidmemory space utilization
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments data into multiple groups (first group, second group, third group) and distributes them across different memory blocks. Parity check codes are generated for each segment independently using XOR operations, allowing error correction at the segment level rather than requiring dedicated parity space for the entire data set. This segmentation enables efficient use of memory space while maintaining error correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent makes data pages serve multiple functions: they store both user data and parity check codes. Specifically, the last data page of each word line is used to store parity check codes generated from other data pages in the same word line. This multi-functionality eliminates the need for separate dedicated parity storage space, thereby improving memory space utilization while maintaining error correction capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If dedicated parity check code storage is implemented, then data reliability is improved, but storage capacity for user data deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoideffective storage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent makes data pages serve multiple functions: they store both user data and parity check codes. Specifically, the last data page of each word line is used to store parity check codes generated from other data pages in the same word line. This multi-functionality eliminates the need for separate dedicated parity storage space, thereby improving memory space utilization while maintaining error correction capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functions of data storage and parity check code storage into the same memory locations. Instead of having separate areas for user data and parity codes, the system combines them by storing parity check codes in the last data page of each word line, which is part of the same memory structure. This merging increases effective storage capacity while maintaining error correction capability.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If RAID-like XOR encoding is implemented across multiple blocks, then memory space utilization is improved, but system complexity increases

Engineering Contradiction:
Improvememory space utilizationVSAvoidencoding operation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments data into multiple groups (first group, second group, third group) and distributes them across different memory blocks. Parity check codes are generated for each segment independently using XOR operations, allowing error correction at the segment level rather than requiring dedicated parity space for the entire data set. This segmentation enables efficient use of memory space while maintaining error correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements self-service by having each memory block generate its own parity check codes using XOR operations on its own data segments. The system uses itself (the data already present in memory blocks) to generate the necessary parity information, eliminating the need for external or complex encoding systems. This self-service approach reduces system complexity while improving memory space utilization.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10236908B2Flash memory apparatus and storage management method for flash memory
Publication Date: 2019.03.19 SILICON MOTION INC
  • US10236908B2 patent drawing
  • US10236908B2 patent drawing
  • US10236908B2 patent drawing

AI summary

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.