Flat BEVA Top Surface Structure for Uniform Memory Electric Fields
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Solution Overview
Problem
The challenge in forming integrated circuits (ICs) is that the metal layer and metal blocking layer have different hardness values, leading to uneven or rough top surfaces of the bottom electrode via (BEVA), resulting in non-uniform electric fields, which affects the yield and performance of memory cells, especially as feature sizes shrink.
Innovation Solution
A method is developed to form a flat BEVA top surface by using a via liner layer and recessing the top surfaces of the lower via body and via liner layer below the via dielectric layer, followed by forming a homogeneous upper via body layer that is planarized to uniformity, ensuring a uniform electric field across the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer and metal blocking layer are used to form the BEVA, then the electrical conductivity and blocking function are improved, but the top surface becomes uneven or rough due to different hardness values
Solution Approach 1:
The BEVA structure is segmented into multiple layers: a via liner layer, a lower via body layer, and an upper via body layer. This segmentation allows each layer to be optimized independently - the via liner provides blocking function, while the via bodies provide conductivity, and the upper via body is specifically designed to provide a flat top surface for memory cell formation.
Solution Approach 2:
Different regions of the BEVA structure are assigned different material properties and functions. The via liner layer has blocking properties, the lower via body has conductivity properties, and the upper via body has both conductivity and surface flatness properties. This local differentiation resolves the contradiction by allowing each region to optimize its specific function without compromising overall performance.
2Productivity
If feature sizes are reduced to increase device density, then the productivity and integration are improved, but the top surface roughness has a greater impact on electric field uniformity and memory cell performance
Solution Approach 1:
The upper via body layer is formed with a flat top surface before the memory cell is fabricated. This preliminary action of creating a flat surface ensures that when the memory cell is subsequently formed at reduced feature sizes, the electric field uniformity is maintained without being adversely affected by surface roughness.
Solution Approach 2:
The patent changes the material parameters and structural parameters of the upper via body layer to achieve a flat top surface. By selecting appropriate materials and deposition parameters, the upper via body is formed with controlled surface topology that maintains electric field uniformity even as overall device dimensions are reduced.
Data Source
AI summary
Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.