Flat BEVA Top Surface Using Recessed Via Layers for Memory
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Solution Overview
Problem
The challenge in forming integrated circuits (ICs) is that the metal layer and metal blocking layer have different hardness values, leading to uneven or rough top surfaces of the bottom electrode via (BEVA), resulting in non-uniform electric fields, which affects the yield and performance of memory cells, especially as feature sizes shrink.
Innovation Solution
A method is developed to form a flat BEVA top surface by using a via liner layer and recessing the top surfaces of the lower via body and via liner layer below the via dielectric layer, followed by forming a homogeneous upper via body layer that fills the opening, ensuring uniform planarization and a flat top surface, thereby achieving a uniform electric field across the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal layer and metal blocking layer are formed with different hardness values, then the BEVA structure can be formed, but the top surface becomes uneven or rough
Solution Approach 1:
The via body is segmented into multiple layers: a lower via body layer formed first, then recessed, and finally filled with an upper via body layer. This segmentation allows different material properties in different regions, with the upper layer providing a flat top surface while the lower layer provides structural support.
Solution Approach 2:
The lower via body layer is formed and recessed below the via dielectric layer top surface before forming the upper via body layer. This preliminary action creates a foundation structure that enables subsequent planarization to achieve a flat top surface.
2Device complexity
If conventional BEVA formation method is used, then manufacturing is simpler, but electric field uniformity deteriorates
Solution Approach 1:
Different regions of the via body are assigned different material properties: the lower via body layer uses one material composition while the upper via body layer uses another. This local differentiation optimizes each region's function, with the upper layer specifically designed to provide a flat surface for uniform electric field distribution.
Solution Approach 2:
The via body is constructed as a composite structure with at least two different materials: the lower via body layer material and the upper via body layer material. This composite approach allows optimization of different properties in different layers, achieving both structural integrity and surface flatness.
3Area of moving object
If feature sizes are reduced, then device density increases, but surface flatness control becomes more difficult
Solution Approach 1:
The invention changes the material parameters of the via body by using different materials for the lower and upper via body layers. This parameter change allows control over the planarization process, enabling achievement of flat top surfaces even as feature sizes shrink and density increases.
Data Source
AI summary
Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.