Flat-Bottom Substrate Warpage Prevention
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Solution Overview
Problem
Semiconductor package substrates experience warpage and cracking issues due to coefficient of thermal expansion (CTE) mismatch, particularly at the lower surface where heat sinks and thermal vias are located, leading to manufacturing complexities and increased costs.
Innovation Solution
A flat-bottom design substrate is implemented where the lower surface is made substantially planar or conformal to the carrier during molding, with solder resist applied in a manner that does not overlap conductive materials, reducing stress and warpage by maintaining a flat surface for component placement and overmolding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress-relieving layers are added to absorb CTE-induced stress, then substrate warpage is reduced, but substrate thickness increases and production complexity increases
Solution Approach 1:
The patent removes the separate stress-relieving layer from the substrate structure and integrates its stress-absorbing function directly into the solder resist coating through a flat-bottom design. This extraction eliminates the need for additional layers while maintaining warpage prevention functionality.
Solution Approach 2:
The patent combines the stress-relieving function with the solder resist coating by designing the bottom surface of the substrate to be substantially flat and coplanar with the solder resist. This merging integrates multiple functions (protection, stress relief, and flatness) into a single structural approach.
2Reliability
If non-functional traces are added to balance stress between surfaces, then warpage is controlled, but manufacturing complexity increases and usable mounting area is reduced
Solution Approach 1:
The patent eliminates the need for non-functional traces by removing the source of unbalanced stress through the flat-bottom design. This extraction removes unnecessary manufacturing steps and materials while achieving stress balance through geometric design rather than trace patterning.
3Reliability
If the bottom surface is made substantially flat and coplanar with solder resist, then warpage and cracking are reduced, but additional processing steps are required
Solution Approach 1:
The patent merges the flatness requirement into the solder resist application process itself, where the solder resist is applied to achieve a coplanar surface. This integration combines the protective coating function with the flatness requirement, reducing the need for separate planarization steps.
4Manufacturing precision
If solder resist is applied to overlap conductive materials, then coverage is improved, but stress concentration and cracking risk increase at thermal vias
Solution Approach 1:
The patent applies local quality by making the solder resist coplanar with the conductive materials rather than overlapping them. This localized adjustment at the interface between solder resist and conductive traces reduces stress concentration points while maintaining adequate coverage in critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces substrate warpage and cracking, improving manufacturing quality and simplifying the process by maintaining a flat surface for component placement and overmolding, while minimizing the need for additional stress-relieving layers.
Implementation Method 1
A heat sink is provided at the lower surface to dissipate heat that is carried by thermal vias extending from the upper surface, through the substrate, to the lower surface. The thermal vias are filled with copper and with epoxy filler.
Implementation Method 2
One major problem that is encountered during package fabrication processes is deformation of the substrate. In addition, cracks are often produced in or near the thermal vias, especially the thermal vias located near to the edge of the heat sink.
Data Source
AI summary
Consistent with an example embodiment, there is an apparatus comprising a circuit (500) board. The circuit board includes a first surface (501a) and a second surface (501b). The first and second surfaces each have at least a component populated thereon; the circuit board has a first surface thereof populated before a second surface thereof and is overmolded. The circuit board has conductive material disposed over areas of the second surface defining at least a feature (504) on the second surface. The at least a feature is defined by the conductive material and other than defined by solder resist (508) disposed on the second surface overlapping the conductive material, wherein the at least a feature is a feature for remaining exposed during a process of populating the first surface other than a fiducial.