Flat Copper Damascene Features With Minimal CMP Dishing

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Solution Overview

Problem

Conventional processes for forming large damascene features in integrated circuits result in significant dishing defects, leading to failure in bonded devices due to unwanted spaces between metal features.

Innovation Solution

The method involves forming large damascene features with different grain sizes in cavities and field regions, where larger grains are formed in cavities and smaller grains in field regions, resulting in a differential removal rate during chemical-mechanical planarization (CMP) that produces flat metal features with minimal dishing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional CMP process is used to planarize copper features, then the copper is removed uniformly, but dishing occurs in larger copper features due to the softer copper material

Engineering Contradiction:
Improveplanarity of metal featuresVSAvoiddishing defect
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies a coating material selectively to different regions (cavities vs. field) to create local quality differences. The coating material has different properties in different locations, causing differential removal rates during CMP that compensate for the inherent dishing tendency of soft copper in large features.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical or chemical parameters of the copper surface by applying a coating material. This coating alters the removal rate parameter during CMP, making it location-dependent and enabling control over the planarization process to prevent dishing.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If copper is deposited to overfill cavities, then the cavities are completely filled, but excessive copper remains on the field requiring removal

Engineering Contradiction:
Improvecavity fill completenessVSAvoidexcessive copper removal
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

The patent performs preliminary action by applying a coating material to the field region before CMP. This pre-coating ensures that when CMP removes excessive copper, the field region is protected or controlled, allowing complete cavity fill while minimizing unnecessary field copper removal.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If large damascene features are formed, then the circuit interconnection capability is improved, but dishing increases with feature width

Engineering Contradiction:
Improveinterconnection capabilityVSAvoidfeature flatness
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent makes different parts of the substrate (cavity regions vs. field regions) have different coating properties. This local quality difference creates location-specific removal rates during CMP that compensate for the width-dependent dishing, enabling large features to maintain flatness while preserving interconnection capability.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach achieves planar metal features across a wide range of sizes, from submicron to over 30 microns, with dishing reduced to less than 10 nm or even less than 3 nm, thereby enhancing the reliability and performance of bonded devices.

Implementation Method 1

The metal is annealed to form larger grains in the cavities and smaller grains in the field regions

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

the metal is planarized, wherein the large metal grains in the cavities are planarized to flat metal features with minimal dishing from the planarization

Methodology Applied
Scientific EffectChemical-mechanical planarization:

Data Source

PatentUS20250022752A1Flat metal features for microelectronics applications
Publication Date: 2025.01.16 ADEIA SEMICON TECH LLC
  • US20250022752A1 patent drawing
  • US20250022752A1 patent drawing
  • US20250022752A1 patent drawing

AI summary

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.