Flat Panel Decoder Layout Using Mixed-Voltage MOSFETs
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Solution Overview
Problem
Conventional decoding circuits for flat panel displays occupy a large area due to the use of numerous MOSFETs, which increases with voltage, hindering miniaturization efforts.
Innovation Solution
The proposed decoding circuit employs a three-decoder structure with low voltage MOSFETs in the first decoder and high voltage MOSFETs in the second decoder, along with a tree-type arrangement of MOSFETs in some embodiments, to reduce the overall area by optimizing MOSFET gate lengths and body voltages, allowing for more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional decoding circuit uses numerous MOSFETs to handle wide voltage range, then voltage selection capability is improved, but circuit area increases significantly
Solution Approach 1:
The decoding circuit is divided into multiple decoders (first decoder, second decoder, third decoder) that process different segments of the voltage selection. Each decoder handles a portion of the voltage range, reducing the number of MOSFETs required in each individual decoder while maintaining the overall voltage selection capability across the full range.
2Reliability
If MOSFET gate length is increased to handle higher voltages, then voltage handling capability is improved, but individual MOSFET area increases
Solution Approach 1:
Different MOSFETs in the circuit are designed with different gate lengths according to their specific voltage handling requirements. MOSFETs handling higher voltages have longer gates, while those handling lower voltages have shorter gates. This localized optimization reduces the overall circuit area compared to using uniformly large MOSFETs throughout.
Solution Approach 2:
The patent introduces a hierarchical decoder structure with multiple levels (first, second, and third decoders) that processes voltage selection in stages. This multi-dimensional approach distributes the voltage handling task across multiple components rather than requiring single large MOSFETs to handle the entire voltage range.
Data Source
AI summary
The present invention relates to a decoding circuit for a flat panel display, and more particularly to a decoding circuit for a flat panel display wherein a miniaturization is possible by reducing an area of the circuit. There is provided a decoding circuit comprising: a first decoder for selecting a predetermined number of gradation voltages from a plurality of gradation voltages according to a least significant bit or least significant bits of an image data; a second decoder for selecting one of the selected gradation voltages to be outputted to an output terminal according to a plurality of selection signals; and a third decoder for outputting the plurality of the selection signals according to a most significant bit or most significant bits of the image data, wherein a minimum length of gates of a plurality of MOSFETs included in the first decoder is shorter than that of a plurality of MOSFETS included in the second decoder.