Flat Panel X-Ray Detector Pixel Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and extended manufacturing cycle time of digital x-ray detectors are primarily due to the complex process of depositing and patterning thin film layers on glass substrates for the imaging panel, which includes multiple layers for FETs and photodiodes, leading to increased production costs and yield reductions.
Innovation Solution
A method of manufacturing a flat panel detector with a silicon FET and diode structure where the full thickness of the gate dielectric and silicon layers remains beneath the diode silicon across the entirety of the detector, with the edges of the diode silicon self-aligned to the underlying FET silicon features, allowing for simultaneous etching of both layers to reduce the number of processing steps and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple thin film layers are deposited and patterned for FETs and photodiodes, then the imaging panel functionality is achieved, but the manufacturing cycle time increases and cost increases
Solution Approach 1:
The patent merges the FET silicon layer and photodiode silicon layer into a single deposited layer. By forming both the FET active region and photodiode region from the same silicon layer, the number of deposition steps is reduced while maintaining the required functionality of both components in the imaging panel
Solution Approach 2:
The single deposited silicon layer serves multiple functions: it forms both the FET transistor structure and the photodiode structure. This multi-functional layer approach eliminates the need for separate deposition processes for each component type, thereby reducing manufacturing cycle time
2Reliability
If multiple thin film layers are deposited and patterned for FETs and photodiodes, then the imaging panel functionality is achieved, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple deposition steps into a single deposition process that creates both FET and photodiode structures. This reduction in the number of processing steps directly lowers manufacturing costs by reducing equipment usage, material waste, and production time
Solution Approach 2:
The invention eliminates redundant processing steps where previously deposited layers would need to be removed or re-deposited. By planning the single layer deposition to accommodate both FET and photodiode structures from the outset, unnecessary manufacturing operations are discarded
3Reliability
If multiple thin film layers are deposited and patterned for FETs and photodiodes, then the imaging panel functionality is achieved, but the manufacturing yield decreases
Solution Approach 1:
By merging the FET and photodiode silicon layers into a single deposited layer, the patent reduces the number of interfaces and processing steps where defects can occur. Fewer deposition and patterning cycles mean fewer opportunities for manufacturing errors, thereby improving overall yield
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cycle time and increases the yield of flat panel x-ray detectors without requiring additional equipment or facility modifications, thereby lowering production costs and improving manufacturing efficiency.
Implementation Method 1
a flat panel detector configured to generate electrical signals in response to incident X-rays
Implementation Method 2
Each additional layer adds to the total manufacturing time (cycle time) and the final yield of the detector; and both cycle time and yield add to the total cost of the detector
Data Source
AI summary
A pixel structure for a flat panel detector is constructed in which the diode silicon and the FET silicon are simultaneously etched to form isolated structures (array photodiodes, I/O elements, and so on) in which the edges or perimeters of the diode silicon features are self-aligned to the underlying FET SI features. The full, as-deposited, thickness of the FET gate dielectric and (at least) part of the FET silicon layer remains underneath the diode silicon across the entirety of the flat panel detector.