Flat Stopper Layers for Microelectronic Memory Devices
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Solution Overview
Problem
Current microelectronic memory devices face challenges in efficiently integrating signal transfer conductive layers and capacitor storage nodes across cell array and peripheral regions, leading to limitations in data transmission and storage capacity.
Innovation Solution
The implementation of a microelectronic substrate with a cell array region and a peripheral region, featuring a lower layer with a flat outer surface, an insulating layer, and a stopper layer, along with signal transfer conductor layers that extend across both regions, and the formation of memory cell capacitor storage nodes that penetrate through the stopper and insulating layers, enhancing data transmission and storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signal transfer conductor layers are extended across both cell array and peripheral regions, then data transmission efficiency is improved, but device complexity increases
Solution Approach 1:
The device is divided into a cell array region and a peripheral region, with the signal transfer conductor layer configured to extend across both regions. This segmentation allows the conductor layer to serve dual functions: signal transfer in the cell array region and peripheral circuit interconnection in the peripheral region, thereby improving data transmission efficiency without proportionally increasing device complexity
Solution Approach 2:
The signal transfer conductor layer is designed to perform multiple functions by extending across both the cell array region and the peripheral region. It serves as both a signal transfer path for memory cells and an interconnection layer for peripheral circuits, reducing the need for separate conductor layers and thus limiting the increase in device complexity
2Quantity of substance
If capacitor storage nodes are formed to penetrate through stopper and insulating layers, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The stopper layer and insulating layer are formed with predetermined thicknesses and material properties before the capacitor storage nodes are formed. The stopper layer, with its specific etch selectivity, serves as a pre-configured barrier that guides the formation of storage nodes penetrating through the insulating layer, ensuring consistent storage capacity while managing manufacturing precision through pre-established structural parameters
3Stability of the object's composition
If flat stopper layers are used across both regions, then structural stability is improved, but ease of manufacture decreases
Solution Approach 1:
The stopper layer is configured with different characteristics in different regions: in the cell array region, it provides flat outer surfaces for structural stability, while in the peripheral region, it is formed to expose signal transfer conductor layers for electrical connection. This local differentiation maintains structural stability where needed while simplifying manufacturing in regions requiring electrical interconnection
Data Source
AI summary
Memory devices comprise a lower layer that extends across a cell array region and across a peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Related methods are also provided.