Flat-Top Bottom Electrodes With Etch Stop Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the lateral dimensions of semiconductor memory cells shrink, the process window for forming contact via structures decreases, leading to an undesired reduction in the thickness of the top electrode during the formation of bottom electrodes and electrode connection via structures, which affects the integrity and density of memory cell arrays.
Innovation Solution
An etch stop dielectric layer is formed over the memory cells to protect the top electrodes during the cutting process of the bottom electrode layer and electrode connection via structure layer, allowing for the preservation of top electrode thickness while forming flat-top bottom electrodes and connection via structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the lateral dimensions of memory cells are reduced to increase density, then the memory cell density is improved, but the process window for forming contact via structures decreases leading to top electrode thinning
Solution Approach 1:
An etch stop layer is formed over the top electrodes before the etching process to create bottom electrodes and contact via structures. This preliminary protective action prevents the etch process from removing top electrode material, thereby maintaining top electrode thickness control while enabling continued scaling for higher memory cell density.
2Ease of manufacture
If the top electrode thickness is reduced due to process constraints, then the fabrication process becomes simpler, but the structural integrity of memory cells deteriorates
Solution Approach 1:
An etch stop layer is introduced as an intermediary protective element between the etch process and the top electrodes. This layer acts as a mediator that allows the etching process to proceed freely to create bottom electrodes and contact via structures while simultaneously protecting the top electrodes from unwanted material removal, thereby maintaining both manufacturing ease and structural integrity.
Data Source
AI summary
A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.