Flat-Top FinFET Epitaxy for Lower S/D Contact Resistance
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Solution Overview
Problem
As semiconductor devices are scaled down, strained source/drain (S/D) contact resistance becomes a prominent factor affecting circuit performance, leading to increased power consumption and reduced circuit speed, as existing S/D formation techniques are not entirely satisfactory in reducing this resistance.
Innovation Solution
The formation of raised S/D features with a substantially flat top surface in FinFETs, achieved by growing epitaxial features that merge from multiple individual features, providing a larger contact area for S/D contacts, which reduces the contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional S/D formation techniques are used, then device scaling is achieved, but S/D contact resistance increases leading to higher power consumption and reduced circuit speed
Solution Approach 1:
Multiple individual epitaxial features are merged to form a single raised S/D feature with a substantially flat top surface. This merging process increases the contact area available for S/D contacts, thereby reducing contact resistance while maintaining scaled device dimensions
Solution Approach 2:
The invention transitions from planar S/D features to three-dimensional raised S/D features with vertical extent. By growing epitaxial features that rise above the substrate surface and merging them, the contact area is increased in the vertical dimension, reducing contact resistance without increasing lateral device footprint
2Reliability
If raised S/D features are formed to reduce contact resistance, then contact area increases, but manufacturing complexity increases
Solution Approach 1:
Epitaxial features are grown in advance before final S/D contact formation. The preliminary growth of multiple individual epitaxial features that will later merge simplifies the overall process by preparing the raised structure with adequate contact area before contact fabrication begins
Solution Approach 2:
The epitaxial growth process automatically merges multiple individual features into a unified raised S/D feature with a flat top surface through self-organization during the growth process. This self-merging behavior reduces the need for additional complex processing steps to achieve the desired geometry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in reduced S/D contact resistance, leading to lower power consumption and faster circuit speed by increasing the contact area between S/D features and contacts, thereby enhancing overall device performance.
Implementation Method 1
strained source/drain (S/D) features (e.g., stressor regions) have been implemented using epitaxial (epi) semiconductor materials to enhance carrier mobility and improve device performance. Forming a MOSFET with stressor regions often epitaxially grows silicon (Si) to form raised S/D features
Data Source
AI summary
A semiconductor device includes a substrate, a semiconductor feature protruding from the substrate and extending lengthwise in a first direction, an epitaxial feature directly above the semiconductor feature, and a gate stack adjacent the epitaxial feature. The epitaxial feature comprises a lower portion and an upper portion over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to the first direction. A topmost surface of the upper portion is substantially flat.