Final Level Cache Controller Address Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing size and number of dynamic random access memories (DRAMs) in devices lead to higher capacitances, longer latency periods, and decreased operating frequencies, making it difficult to reduce package size while maintaining storage capacity, and resulting in higher costs and power consumption.
Innovation Solution
A data access system that includes a final level cache module with a DRAM and a DRAM controller, which converts physical addresses to virtual addresses and back to physical addresses to optimize memory access, reducing the need for direct DRAM access and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size and number of DRAMs are increased to maintain storage capacity, then storage capacity is improved, but capacitance increases, latency period increases, and operating frequency decreases
Solution Approach 1:
The patent segments the memory system into multiple levels: L0 cache within the processor, L1/L2 caches on the SoC, and external DRAMs. This segmentation allows each level to have optimized characteristics - small fast caches close to the processor and larger slower DRAMs for bulk storage, thereby maintaining high operating frequencies for critical operations while providing large total storage capacity.
Solution Approach 2:
The patent introduces cache memory as an intermediary between the processor and external DRAMs. The cache acts as a buffer that stores frequently accessed data closer to the processor, reducing the need for high-speed access to large DRAMs. This allows the system to use larger DRAMs for capacity while maintaining high operating frequencies through the cache intermediary.
2Quantity of substance
If the size and number of DRAMs are increased to maintain storage capacity, then storage capacity is improved, but latency period increases
Solution Approach 1:
The memory hierarchy segments storage into multiple levels with different latency characteristics. The L0 and L1 caches provide low-latency access for frequently used data, while larger capacity DRAMs handle less frequently accessed data. This segmentation ensures that the increased DRAM capacity does not degrade the latency for critical operations.
Solution Approach 2:
The cache memory performs preliminary action by pre-loading and storing frequently accessed data and instructions in the L0 and L1 caches before they are needed by the processor. This preliminary positioning of data reduces the latency period when the processor needs to access this data, even though the total storage capacity is provided by larger external DRAMs.
3Quantity of substance
If the size and number of DRAMs are increased, then storage capacity is improved, but package size becomes difficult to reduce
Solution Approach 1:
The patent segments the memory system into integrated caches on the SoC and external DRAMs, allowing the critical high-speed cache portion to be compact and integrated while the bulk storage DRAMs can be optimized for capacity. This segmentation enables reducing the package size of the critical path components while maintaining large total storage capacity through the external DRAMs.
4Quantity of substance
If the size and number of DRAMs are increased, then storage capacity is improved, but power consumption increases
Solution Approach 1:
The memory hierarchy segments storage into small integrated caches and larger external DRAMs. The processor primarily accesses the small, low-power caches for frequently used data, avoiding the need to continuously power and access the larger, higher-power DRAMs. This segmentation reduces overall power consumption while maintaining large storage capacity.
Solution Approach 2:
The cache memory acts as an intermediary that reduces power consumption by intercepting and satisfying memory access requests for frequently accessed data. This prevents the need to continuously access the power-hungry external DRAMs, thereby reducing overall system power consumption while maintaining large storage capacity through the DRAMs.
Data Source
AI summary
A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.