Fletcher Checksum SIMD Pipeline Using Add-Shift Transformation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The determination of Fletcher/Alder checksums using single SIMD pipeline processors is inefficient due to sub-optimal performance, leading to performance bottlenecks in data integrity checking applications.
Innovation Solution
A method that transforms the generation of Fletcher/Alder checksums from requiring integer multiplications and additions to only integer additions and shifts, allowing their use on single SIMD pipeline processors by accumulating and scaling partial checksums, thereby improving processor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Fletcher/Alder checksums are implemented using standard integer multiplications and additions on single SIMD pipeline processors, then the checksum generation can be performed, but the processor performance deteriorates due to sub-optimal performance and performance bottlenecks
Solution Approach 1:
The patent transforms the checksum generation algorithm by changing the mathematical parameters from requiring integer multiplications and additions to only requiring integer additions and shifts. This parameter transformation enables the algorithm to run efficiently on single SIMD pipeline processors, resolving the performance bottleneck while maintaining checksum generation capability
Solution Approach 2:
The patent substitutes the traditional integer multiplication and addition operations with integer addition and bit shift operations. This substitution replaces computationally expensive operations with simpler, faster operations that are more suitable for SIMD pipeline architecture, thereby improving processor performance and eliminating the performance bottleneck
2Productivity
If the coupling between the two partial checksums is broken to allow SIMD pipeline implementation, then parallel processing capability is improved, but the checksum accuracy deteriorates
Solution Approach 1:
The patent introduces intermediate variables and transformation steps that act as mediators between the broken coupling of partial checksums and the final accurate checksum result. These intermediaries preserve the mathematical relationship needed for accuracy while enabling parallel SIMD processing of the decoupled components
Solution Approach 2:
The patent performs preliminary transformations on the partial checksums before they are combined, preparing them in advance so that when the decoupled SIMD results are merged, the final checksum accuracy is maintained. This preliminary action ensures that the broken coupling during processing does not compromise the final result
Data Source
AI summary
The generation of Fletcher/Alder partial checksums are transformed from a space that requires integer multiplications and additions to a space that requires only integer additions and shifts on a single SIMD pipeline capable processor. This transformation permits the use of Fletcher/Alder checksums on processors where the performance of SIMD instructions are sub-optimal, on CMT processors that support a single SIMD pipeline as well as other processors that can be configured by executing software to implement SIMD operations for a single SIMD pipeline. The implementation of the process with this transformation on a general-purpose computer system transforms that general-purpose computer system into a special-purpose computer system that uses a single SIMD pipeline to generate a Fletcher/Alder checksum. The elimination of integer multiplications in the generation of the partial checksums results in a significant improvement in performance.