Flex Bus Protocol Negotiation for Interconnect Adaptability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current interconnect architectures, such as PCIe and QPI, face challenges in providing optimal performance and power efficiency across different market segments, with servers requiring high performance and mobile ecosystems prioritizing power savings, while also needing to support various interconnect protocols and protocols like IAL.io, IAL.cache, and IAL.mem for coherent memory access.
Innovation Solution
The introduction of a flex bus negotiation sequence using PCIe alternate protocol negotiation mechanisms to dynamically select and enable protocols like IAL, GenZ, CAPI, or OpenCAPI over PCIe electricals, allowing for multiplexing of multiple protocols on a single set of pins, and enabling latency optimizations such as sync header suppression and skip ordered set suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single interconnect architecture is used across different market segments, then device complexity is reduced, but performance and power efficiency cannot be optimized for specific market needs
Solution Approach 1:
The flex bus interface is designed to support multiple interconnect protocols (PCIe, CAPI, GenZ, IAL) over a single physical interface. The system can dynamically negotiate and switch between different protocols based on market segment requirements, allowing one interface to serve multiple functions and eliminating the need for separate dedicated interfaces for each protocol type
Solution Approach 2:
The interconnect architecture implements dynamic protocol negotiation and switching capabilities. The system can adaptively select and transition between different protocols (PCIe, CAPI, GenZ, IAL) based on real-time requirements, enabling the interface to change its operational mode dynamically rather than being fixed to a single protocol
2Adaptability or versatility
If multiple protocols are supported on a single flex bus, then adaptability improves, but protocol negotiation and switching complexity increases
Solution Approach 1:
The system performs protocol capability advertisement and negotiation during the link training phase, before actual data transmission begins. This preliminary action allows both ends to agree on the supported protocol and configure the interface accordingly, avoiding the need for complex runtime protocol switching and reducing overall system complexity
3Productivity
If standard PCIe protocol is used, then compatibility is maintained, but latency cannot be optimized for high-performance applications
Solution Approach 1:
The system changes the protocol parameters by transitioning from standard PCIe to alternative protocols (CAPI, GenZ, IAL) that offer lower latency characteristics. These alternative protocols modify key parameters such as packet formatting, error handling mechanisms, and flow control to reduce overhead and achieve lower latency for high-performance applications
4Productivity
If protocol switching is implemented, then performance optimization is enabled, but link training and initialization time increases
Solution Approach 1:
The system performs protocol capability advertisement and selection during the initial link training phase, so that the optimal protocol is determined before data transmission begins. This preliminary protocol negotiation prevents the need for time-consuming protocol switching during operation, as the system is already configured for optimal performance from the start
Data Source
AI summary
Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.