Clock Synchronization in Flexible Ethernet Networks
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Solution Overview
Problem
In flexible Ethernet (FlexE) networks, the variable mapping of data blocks across multiple physical layer modules (PHYs) leads to skew between data blocks from the same client, making it difficult to accurately determine the receiving time of clock synchronization packets, as the transmission sequence changes and the mapping relationship is unpredictable.
Innovation Solution
The receiving apparatus performs timestamp sampling on received data blocks to generate aligned receipt timestamps, using a reference timestamp from the first PHY that receives an overhead block to correct skew, allowing for accurate determination of the clock synchronization packet's receiving time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data blocks are transmitted using multiple PHYs with variable mapping, then transmission bandwidth and rate are improved, but skew occurs between data blocks from the same client making clock synchronization difficult
Solution Approach 1:
The patent introduces an overhead frame as an intermediary carrier that transports timing reference information (such as send time timestamps) alongside data blocks. This overhead frame acts as a mediator that enables the receiving end to identify and correct skew between data blocks from the same client, even when they are transmitted through different PHYs with variable mapping relationships.
Solution Approach 2:
The patent applies preliminary action by embedding timing reference information (send time timestamps) into the overhead frames before data block transmission. This advance preparation allows the receiving end to predict and correct arrival time skew without requiring complex real-time synchronization mechanisms, thus maintaining high transmission bandwidth while improving receiving time determination accuracy.
2Adaptability or versatility
If mapping relationship changes during transmission, then flexibility and adaptability are improved, but skew amount becomes unpredictable preventing accurate receiving time determination
Solution Approach 1:
The patent implements feedback by including send time timestamps in the overhead frames that travel with data blocks. The receiving end uses these timestamps to calculate actual transmission delays and skew amounts, then feeds this information back to adjust the receiving time determination. This closed-loop feedback mechanism maintains mapping flexibility while ensuring accurate receiving time determination even when mapping relationships change dynamically.
Data Source
AI summary
A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.