FlexE Clock Synchronization via Data Block Timestamp Sampling
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Solution Overview
Problem
The existing clock synchronization methods in Flexible Ethernet (FlexE) are limited by fixed overhead frame formats and bandwidth, restricting clock synchronization frequency and scalability, and are not compatible with conventional Ethernet standards due to unordered data block arrival sequences caused by time division multiplexing.
Innovation Solution
The method involves generating indication information to identify pre-agreed data blocks for timestamp sampling, allowing clock synchronization packets to be sent and received in non-overhead frames, increasing frequency and bandwidth, and maintaining compatibility with conventional Ethernet standards by using client payloads and timestamp sampling similar to conventional Ethernet methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock synchronization packets are transmitted through the management channel of overhead frames in FlexE, then clock synchronization can be implemented, but the fixed format and bandwidth of overhead frames limit clock synchronization frequency and scalability
Solution Approach 1:
The patent introduces indication information as an intermediary mechanism that enables the system to dynamically identify and select specific data blocks for timestamp sampling. This intermediary allows the clock synchronization function to operate flexibly within the FlexE framework without being constrained by the fixed overhead frame structure, thereby increasing synchronization frequency and scalability while maintaining compatibility with existing FlexE protocols
2Productivity
If data blocks are mapped by time division multiplexing layer in FlexE, then bandwidth utilization is improved, but data blocks arrive at MDI in disordered sequence making timestamp sampling impossible
Solution Approach 1:
The patent implements a feedback mechanism where the receiving apparatus sends indication information back to the sending apparatus, identifying which data blocks should be used for timestamp sampling. This feedback loop allows the system to maintain the benefits of time division multiplexing for bandwidth utilization while ensuring that the correct data blocks are selected for synchronization, even when they arrive in disordered sequences
Solution Approach 2:
Indication information serves as an intermediary that bridges the gap between the disordered data block arrival caused by time division multiplexing and the requirement for ordered timestamp sampling. The indication information carries identification data that allows the receiving apparatus to correctly associate timestamps with the appropriate data blocks despite the reordering
3Adaptability or versatility
If conventional Ethernet clock synchronization method is applied to FlexE, then compatibility with existing standards is achieved, but the method cannot determine which data block is pre-agreed due to unordered arrival
Solution Approach 1:
The patent uses indication information as a form of 'color coding' or identification marker that distinguishes the pre-agreed data block from other data blocks in the FlexE stream. This identification mechanism allows the system to maintain compatibility with conventional Ethernet clock synchronization methods while providing the additional capability to identify specific data blocks even when they arrive in disordered sequences due to time division multiplexing
Data Source
AI summary
This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.