Flexible Address Mapping for Programmable Logic Arrays
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Solution Overview
Problem
Existing programmable processing devices face inefficiencies when mapping digital peripheral functions with wider widths than the programmable digital blocks, leading to resource wastage or complex access interactions due to alignment and address decoding limitations.
Innovation Solution
A flexible address mapping scheme is implemented, where digital peripheral functions are mapped to contiguous universal digital blocks based on access mode widths, allowing for aligned access and efficient resource utilization by choosing memory addresses as multiples of a ratio between the access mode width and the block width, enabling atomic register access across varying access modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a 16-bit digital peripheral function is mapped to programmable digital blocks starting with an even memory address, then the CPU can access the mapped function in one cycle via aligned access, but it results in wasted resources because the function cannot be mapped to start with an odd memory address
Solution Approach 1:
The patent implements dynamic address decoding that adapts to the width of the digital peripheral function. The system determines whether to use even or odd address alignment based on the function width, allowing the addressing scheme to change behavior dynamically rather than being fixed. This enables 16-bit functions to be mapped to odd addresses when appropriate, while still maintaining efficient CPU access through width-matched decoding.
Solution Approach 2:
The invention changes the address decoding parameters based on the digital peripheral function width. The address decoder is configured with different decoding modes (even-aligned or odd-aligned) depending on whether the function is 8-bit, 16-bit, or wider. This parameter change allows the system to optimize both resource utilization and CPU access efficiency for different function widths.
2Adaptability or versatility
If a 16-bit digital peripheral function is mapped to programmable digital blocks starting with an odd memory address, then the function can be mapped to start in any block, but it forces the CPU to break up access into multiple access cycles at aligned boundaries
Solution Approach 1:
The address decoding system dynamically adjusts its behavior based on the mapped function's width. When a 16-bit function is mapped to odd addresses, the decoder is configured to perform width-matched decoding that allows the CPU to access the full 16-bit width in a single cycle, rather than forcing broken accesses. This dynamic adaptation eliminates the need for multiple access cycles while maintaining mapping flexibility.
3Device complexity
If the address width of the programmable digital block is fixed, then the block structure is simple, but it cannot efficiently handle digital peripheral functions with varying widths
Solution Approach 1:
The patent implements a universal address decoding scheme that can handle digital peripheral functions of various widths (8-bit, 16-bit, and wider) using the same programmable digital block structure. The address decoder is designed to be configurable and can adapt its decoding width based on the function being mapped, making the fixed-width blocks universally applicable to different function widths without requiring multiple specialized block types.
Data Source
AI summary
A method for implementing an addressing scheme may include mapping a digital peripheral function to one or more contiguous configurable blocks in an array of configurable blocks; and assigning a memory address from a plurality of memory addresses to at least one register of each of the one or more contiguous configurable blocks based on an access mode width of the digital peripheral function and a width of each of the one or more contiguous configurable blocks.