Flexible Cache Structure for Compressed and Uncompressed Cachelines
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Solution Overview
Problem
Existing cache structures are either inflexible or wasteful in handling compressed and uncompressed data, leading to inefficiencies in silicon area usage and increased power consumption.
Innovation Solution
A cache structure that allows flexible storage of cachelines in different formats by selecting between a first mode for uncompressed data and a second mode for compressed data, utilizing a second RAM that can act as both tag RAM and data RAM, with configurable modes for individual cache entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a cache structure uses fixed-width fields for storing cachelines and tags, then the cache structure is simple and regular, but it cannot flexibly store compressed and uncompressed data, leading to wasted silicon area
Solution Approach 1:
The cache structure dynamically configures the width of data RAM fields and tag RAM fields based on whether compressed or uncompressed data is being stored. The circuitry determines the data format and adjusts the field widths accordingly, allowing the same physical storage resources to be optimally utilized for different data types without wasting silicon area.
Solution Approach 2:
The patent changes the parameter of field width in the RAM structures based on the data compression state. When storing uncompressed cachelines, the data RAM fields are configured to the full architectural width. When storing compressed cachelines, the field width is reduced to match the compressed data size, thereby reducing the required silicon area while maintaining full functionality.
2Area of stationary object
If the second RAM is used as both tag RAM and data RAM, then silicon area is reduced, but the cache structure becomes more complex in terms of mode selection and configuration
Solution Approach 1:
The second RAM is designed to serve multiple functions: it can operate as tag RAM when storing compressed cachelines and as data RAM when storing uncompressed cachelines. This multi-functionality is achieved through mode selection circuitry that configures the second RAM's operation based on the data format, allowing one physical memory structure to replace what would traditionally require two separate memory structures.
Solution Approach 2:
The cache structure includes dynamic mode selection and configuration circuitry that adapts the operation of the second RAM based on whether the cached data is compressed or uncompressed. This dynamic reconfiguration allows the same hardware resources to be optimally utilized for different data formats, reducing overall cache complexity despite the added flexibility.
3Quantity of substance
If compressed data is cached, then the cache capacity is effectively increased, but the power consumption increases due to compression and decompression operations
Solution Approach 1:
The cache structure applies compression selectively rather than universally. The circuitry determines which cachelines are suitable for compression and applies compression only to those that benefit from it, leaving other cachelines in uncompressed form. This local application of compression reduces unnecessary power consumption while still achieving capacity benefits for compressible data.
Solution Approach 2:
The system dynamically changes the compression parameter based on the characteristics of the data being cached. By analyzing the cacheline content and determining the appropriate compression level or whether compression is beneficial, the system optimizes the balance between cache capacity and power consumption, avoiding unnecessary compression operations.
4Adaptability or versatility
If the cache structure supports both compressed and uncompressed data formats, then versatility is improved, but the difficulty of detecting and measuring data format increases
Solution Approach 1:
The cache structure determines the data format (compressed or uncompressed) before the cacheline is actually stored in the cache. This preliminary format detection allows the cache circuitry to be pre-configured with the appropriate field widths and access parameters, simplifying subsequent read and write operations. The format information is captured and stored alongside the cacheline, making it easily retrievable without complex detection during access operations.
Data Source
AI summary
A device in which each field in a first RAM together with a respective field in a second RAM form a respective entry of a cache RAM. Caching circuitry is operable to use the respective field in the first RAM to hold a first portion of a single cacheline, and the respective field in the second RAM to hold the corresponding tag of the single cacheline and a remaining portion of the single cacheline. The caching circuitry is further arranged so as, upon a cache hit by a subsequent memory access operation requesting to access data for which a corresponding cacheline has already been cached, to retrieve the corresponding tag and the remaining portion of the respective cacheline from the second RAM in a first one of a sequence of clock cycles.