Flexible Calculation Unit for Hearing Aid Signal Processing
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Solution Overview
Problem
Contemporary hearing aids face challenges in minimizing digital chip area while maintaining high frequency resolution and low processing delay, leading to increased costs and resource requirements.
Innovation Solution
A flexible calculation unit that can perform both complex and real-valued multiplications, reducing chip area usage by 50% through efficient reuse of complex multiplier resources for various calculations, including FFT operations and window operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If separate complex and real multipliers are used for FFT and window operations, then processing capability is sufficient, but chip area increases by 50%
Solution Approach 1:
The complex multiplier unit is designed to perform both complex multiplication (for FFT operations) and real multiplication (for window operations) by reconfiguring its internal structure. The same hardware resources are dynamically allocated to different mathematical operations based on the current processing stage, eliminating the need for separate dedicated multiplier units for each operation type.
Solution Approach 2:
The calculation unit employs dynamic reconfiguration where the operational mode (complex or real multiplication) is changed in real-time based on the processing requirements. Control logic dynamically switches the multiplier between different computational modes, allowing the hardware to adapt its functionality to match the current algorithmic needs of the signal processing pipeline.
2Measurement precision
If high frequency resolution is achieved through advanced signal processing, then analysis precision improves, but processing delay increases
Solution Approach 1:
The system pre-calculates and stores window function values in memory before they are needed for the actual signal processing. By preparing these computational elements in advance, the system eliminates the need for real-time computation of window functions during critical signal processing stages, thereby reducing processing delay while maintaining high frequency resolution capabilities.
3Speed
If dedicated hardware units are implemented for each signal processing operation, then processing speed is sufficient, but device complexity and cost increase
Solution Approach 1:
The calculation unit is designed as a universal processor that can execute multiple types of mathematical operations (complex multiplication, real multiplication, and other signal processing functions) using the same hardware resources. This multi-functional design reduces the total number of dedicated hardware units required, thereby lowering device complexity and cost while maintaining adequate processing speed through efficient resource utilization.
Data Source
AI summary
A hearing aid having a digital processing unit (200) having at least four digital data inputs configured to provide four input signals, at least two digital data outputs configured to provide two output signals, and a calculation unit (100) having at least one switch and at least one first multiplexer configured to route the input signals from the digital data inputs to the digital data outputs. The first configuration of the at least one switch and the at least one first multiplexer provides a complex multiplication of the four input signals representing two complex numbers, and a second configuration of the at least one switch and the at least one first multiplexer provides parallel real multiplication of two pairs of input signals the four input signals representing four real numbers.