Flexible Carrier Semiconductor Package for 3D Chip Stacking
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Solution Overview
Problem
Existing semiconductor package devices face challenges with large size, increased power consumption, warpage, and high material costs due to rigid carriers and complex packaging processes, particularly in 2D, 2.5D, PoP stacked, and 3D package structures, which hinder efficient space utilization and structural rigidity.
Innovation Solution
A semiconductor package device utilizing a flexible carrier with a patterned build-up circuit and integrated rigid layers, allowing for 3D stacking and simplifying the packaging process by using a flexible part to connect chips and modules with different heights without requiring a circuit board or interposer, thereby reducing package volume and improving structural strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are arranged horizontally on the same carrier in a 2D package structure, then the package device can accommodate multiple chips, but the carrier length increases resulting in a larger package size
Solution Approach 1:
The patent transitions from a 2D horizontal arrangement of chips on a carrier to a 3D stacked arrangement where chips are vertically positioned above each other. This dimensional change allows multiple chips to be integrated without increasing the carrier's horizontal length, thereby reducing the overall package footprint while accommodating the same number of chips.
Solution Approach 2:
The patent employs a flexible carrier that can be bent at least 180 degrees, allowing the carrier to conform to the vertical stacking arrangement of chips. This flexibility enables the carrier to connect chips at different heights without requiring a large horizontal area, thus reducing the package size while maintaining electrical connectivity.
2Quantity of substance
If the carrier length is increased to accommodate multiple chips horizontally, then all chips can be carried on the same carrier, but the conductive layer length increases resulting in higher power consumption
Solution Approach 1:
By arranging chips vertically in a stacked configuration rather than horizontally, the patent significantly reduces the horizontal distance that electrical signals must travel through the conductive layers. This dimensional reorganization shortens the conductive path length, thereby reducing power consumption while still accommodating multiple chips on the same carrier.
Solution Approach 2:
The flexible carrier enables short vertical interconnections between stacked chips, minimizing the length of conductive paths required for signal transmission. This reduces the overall power consumption of the package device compared to horizontal arrangements where conductive layers must span the entire carrier length.
3Quantity of substance
If multiple chips are carried on the same carrier, then integration is achieved, but the carrier is prone to warpage and yield rate decreases
Solution Approach 1:
The patent reduces carrier warpage by transitioning to a vertical stacking architecture. This dimensional change distributes the mechanical stress and thermal expansion forces more evenly across the carrier structure, preventing the cumulative warpage effects that occur when multiple heavy chips are mounted horizontally on a single large carrier.
Solution Approach 2:
The flexible carrier is designed with enhanced mechanical properties that allow it to accommodate vertical chip stacking without warping. The flexibility enables the carrier to absorb thermal and mechanical stresses from the stacked chips, maintaining structural integrity and improving manufacturing yield rate compared to rigid carriers in horizontal configurations.
4Strength
If a silicon interposer is added to increase overall rigidity in a 2.5D package structure, then structural stability is improved, but material costs and packaging process complexity increase
Solution Approach 1:
The patent integrates the carrier and interposer functions into a single flexible carrier structure, eliminating the need for a separate silicon interposer. This merging of functions maintains the structural rigidity needed for vertical chip stacking while simplifying the packaging process and reducing material costs associated with multiple discrete components.
Solution Approach 2:
The flexible carrier is designed to perform multiple functions simultaneously: providing mechanical support for vertical chip stacking, enabling electrical interconnections through integrated conductive paths, and offering thermal management capabilities. This multi-functionality replaces the specialized silicon interposer, reducing device complexity and manufacturing cost while maintaining structural integrity.
5Volume of moving object
If chips are stacked vertically in a PoP package structure, then space utilization is improved, but heat dissipation becomes difficult and temperature increases
Solution Approach 1:
The flexible carrier incorporates integrated thermal management features such as thermally conductive pathways and heat dissipation structures that extend vertically through the stacked chip configuration. These flexible thermal management components maintain close thermal contact with each chip, enabling effective heat extraction from the compact vertical arrangement without requiring additional external cooling systems.
Solution Approach 2:
The patent employs composite materials in the flexible carrier that combine high thermal conductivity with mechanical flexibility. These composite structures enable efficient heat transfer from the stacked chips to external heat sinks or cooling systems, solving the heat dissipation challenge inherent in vertical stacking while maintaining the compact package volume.
6Strength
If a rigid carrier is used to provide structural support, then carrier strength is maintained, but the package device size increases and flexibility is reduced
Solution Approach 1:
The patent replaces traditional rigid carriers with a flexible carrier that can be bent at least 180 degrees. This flexible carrier maintains sufficient structural strength to support vertically stacked chips through its engineered mechanical properties and geometry, while its flexibility allows it to conform to compact packaging requirements, thereby reducing the overall package size compared to rigid carrier configurations.
Solution Approach 2:
By transitioning from horizontal chip arrangement on a rigid carrier to vertical stacking on a flexible carrier, the patent reduces the horizontal footprint of the package. The flexible carrier's ability to accommodate vertical stacking without requiring large horizontal area significantly reduces package size while maintaining the necessary structural support through three-dimensional structural design.
Data Source
AI summary
A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.