Flexible Circuit Carrier Assembly With Embedded Interconnects
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Solution Overview
Problem
Existing connectors in circuit carriers face contact resistance issues due to multi-interface degradation, hindering miniaturization, higher speed, and better electrical performance in high-performance computing systems.
Innovation Solution
A flexible circuit carrier structure is developed with a dielectric layer and conductive patterns, featuring a multi-layered construction with pre-patterned dielectric and conductive layers, allowing for improved electrical connections and reduced contact resistance through conductive vias and through holes, enhancing folding endurance and flexural properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing connectors are used in circuit carriers, then electrical connections can be established, but contact resistance increases due to multi-interface degradation
Solution Approach 1:
The patent merges the connector function directly into the circuit carrier by integrating conductive patterns and contact pads onto the same substrate. This eliminates separate connector components and their associated interfaces, thereby reducing contact resistance caused by multi-interface degradation while maintaining reliable electrical connections.
Solution Approach 2:
The patent extracts the connector functionality from separate physical components and integrates it directly into the circuit carrier substrate through printed conductive patterns. This removal of discrete connector elements eliminates the additional interfaces that cause contact resistance, while the conductive patterns provide the necessary electrical connection pathways.
2Volume of moving object
If miniaturization is pursued in electronic devices, then device size is reduced, but electrical performance degrades due to increased transmission loss and insertion loss
Solution Approach 1:
The patent changes the electrical parameters of the circuit carrier by using optimized conductive pattern geometries, controlled impedance designs, and adjusted trace widths. These parameter changes reduce transmission loss and insertion loss, enabling miniaturized devices to maintain high-speed electrical performance despite reduced size.
Solution Approach 2:
The patent employs composite material structures in the circuit carrier, combining dielectric layers with optimized conductive patterns. This composite construction allows for reduced signal loss by carefully selecting material properties such as dielectric constant and loss tangent, enabling miniaturization while preserving electrical performance.
3Reliability
If additional connectors are added to improve electrical connections, then contact resistance is reduced, but device complexity and size increase
Solution Approach 1:
The patent makes the circuit carrier multi-functional by integrating both the signal transmission function and the electrical connection function into a single component. The conductive patterns on the circuit carrier serve dual purposes: routing signals and providing connection interfaces, thereby eliminating the need for additional dedicated connectors and reducing overall device complexity.
Data Source
AI summary
An electronic assembly includes a first wafer including a stack of alternating first dielectric layers and first circuit layers, a flexible structure including a second dielectric layer and a second circuit layer covered by the second dielectric layer, and a second wafer stacked upon the first wafer and including chip packages arranged in an array. The flexible structure includes a first region embedded in the first wafer and a second region connected to the first region and extending out from an edge of the first wafer. The chip packages are electrically coupled to the second circuit layer of the flexible structure through the first circuit layers of the first wafer.