Flexible Chip Packaging Substrate With Through-Substrate Leads
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Solution Overview
Problem
In chip packaging structures, the increasing number of test pads due to shrinking IC chip sizes leads to smaller test pad dimensions, causing inaccurate testing results due to probe slippage, especially in densely packed arrangements where limited space restricts pad size and leads occupy valuable area.
Innovation Solution
The chip packaging substrate features a flexible substrate with test pads arranged in multiple rows, where leads connected to the middle row extend through the substrate, allowing larger test pad dimensions and reducing the likelihood of probe slippage by increasing layout space in the test pad area, with sections of leads on opposite surfaces avoiding space occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of test pads is increased to accommodate shrinking IC chip sizes, then the integration density is improved, but the test pad dimensions become smaller leading to inaccurate testing
Solution Approach 1:
The patent applies dimensionality change by routing leads through the flexible substrate to the rear surface, effectively utilizing the third dimension (depth/through-thickness direction) to relocate lead positions. This allows test pads on the front surface to be enlarged without being constrained by lead space occupation, thereby resolving the contradiction between increased test pad quantity and maintained test pad dimensions for accurate probing.
2Quantity of substance
If test pads are arranged in multi-row stepped arrangement to accommodate more pads in limited space, then the quantity of test pads is improved, but the test pad dimensions become smaller
Solution Approach 1:
The patent utilizes the through-substrate dimension by having leads penetrate the flexible substrate and emerge on the rear surface. This dimensional relocation allows test pads on the front surface to occupy full available area without being encroached upon by leads, enabling both high quantity of test pads and sufficient individual pad area for reliable probing.
3Area of stationary object
If leads are positioned close to test pads to save space, then the space utilization is improved, but probe slippage occurs on small test pads
Solution Approach 1:
The patent extracts leads from the front surface test pad area and relocates them to the rear surface of the flexible substrate. This separation removes the harmful factor (leads occupying test pad space) and allows test pads to be significantly enlarged, ensuring reliable probe contact while maintaining efficient space utilization on the front surface.
4Reliability
If test pads are enlarged to prevent probe slippage, then the testing reliability is improved, but the number of test pads that can be accommodated decreases
Solution Approach 1:
The patent resolves this contradiction by utilizing the through-substrate dimension to relocate leads to the rear surface. This enables test pads on the front surface to be enlarged for reliable probing while simultaneously accommodating a high quantity of test pads, as the lead routing no longer competes for front surface space.
Data Source
AI summary
A chip packaging substrate includes a flexible substrate, a plurality of test pads, and a plurality of leads, wherein the flexible substrate has a first surface and a second surface, and the first surface has a user area and a test pad area configured thereon. The test pads are arranged in at least three rows within the test pad area. The lead connected to the test pad in the middle row includes a first section extending from the chip to the test pad area and a second section disposed on the second surface, wherein one end of the second section penetrates the flexible substrate to connect with the first section and the other end penetrates the flexible substrate to connect with the test pad, so as to increase the dimensions of the test pads.