Flexible Scaffold Chiplet Interconnect Layouts for Multi-Die Packages
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Solution Overview
Problem
Designing and implementing package layouts for multi-die packages with programmable devices is challenging due to increased wire density and complexity, making testing and validation difficult, especially when components are manufactured by different vendors and use different communication protocols.
Innovation Solution
A scaffold interconnect network (FlexSCI) provides a common specification for designing multi-chip packages with a flexible and scalable interconnect fabric that includes nodes for signal transfer, protocol translation, security, and debugging, along with a compiler that generates efficient package layouts using a connectivity graph.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wire density is increased to facilitate more interconnects for data routing, then the number of available interconnects increases, but design complexity increases
Solution Approach 1:
The patent segments the high-density interconnect grid into manageable units by introducing switch blocks that divide and control signal routing. This segmentation allows the complex wiring infrastructure to be organized into discrete, controllable segments rather than a monolithic complex structure.
Solution Approach 2:
Switch blocks serve as intermediary elements between the high-density interconnect grid and the logic components. These intermediaries manage the complexity by providing controlled access points and routing logic, shielding designers from the full complexity of the dense interconnect network.
2Quantity of substance
If pitch size of D2D interconnects is decreased to increase wire density, then more interconnects are available, but space within programmable devices increases
Solution Approach 1:
The patent transitions from planar 2D routing to three-dimensional routing by implementing vertical interconnect access through multiple layers. This dimensional change allows more interconnects to be packed into the same footprint by utilizing the vertical dimension for signal routing.
Solution Approach 2:
The interconnect structure implements nested routing where multiple routing layers are stacked vertically, with each layer containing interconnects that can be accessed through vias and through-silicon vias. This nesting allows dense packing of interconnects without increasing the lateral footprint.
3Adaptability or versatility
If multiple integrated circuit devices are included in a package with different vendors and protocols, then functionality is enhanced, but designing package layouts becomes difficult
Solution Approach 1:
The patent implements a universal interconnect architecture with standardized switch blocks and routing structures that can accommodate multiple protocols and vendor-specific components. This universal framework provides a common interface layer that abstracts away protocol differences, allowing multi-vendor integration without proportionally increasing design complexity.
Data Source
AI summary
Systems or methods of the present disclosure may provide a compiler that generates a package layout for a multi-die package based on a common specification provided by a Flexible Scaffold Chiplet Interconnect (FlexSCI). The compiler may generate a scaffold interconnect network formed by a subset of interconnects provided by integrated circuits within the multi-die package. The compiler may also identify and/or assign a functionality to nodes of the scaffold interconnect network. The nodes may route data, verify and/or validate, and/or debug dies within the multi-die package. Then, the compiler may identify a position of each die within the scaffold interconnect network. The compiler may instruct a display to display the package layout and/or automatically implement the package layout on a multi-die package via a system design configuration. As such, the systems and methods of the present disclosure may simplify the design process for multi-die packages.