Flexible Clock Placement in PLDs Using Integer Linear Programming
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Solution Overview
Problem
The clock placement problem in programmable logic devices (PLDs) is challenging due to the high cost and power consumption of global clock trees, limiting the number of global clock networks, and existing approximation and heuristic algorithms often fail to find a feasible solution, making manual floor-planning cumbersome and time-consuming.
Innovation Solution
The use of Integer Linear Programming (ILP) to formulate and solve the clock placement problem, allowing for flexible clock placement by defining virtual clock regions and objective functions that minimize physical clock regions and regulate the distribution of global clock networks among physical clock regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If global clock trees are implemented to support more global clock networks, then the number of global clock networks increases, but device area and power consumption increase significantly
Solution Approach 1:
The patent divides the device into multiple clock regions, each with its own limited set of global clock trees. This segmentation allows different regions to use different clock networks, enabling support for more total clock networks across the device without requiring all regions to have access to all clock trees, thus reducing overall area requirements.
Solution Approach 2:
Each clock region is configured with specific clock drivers and global clock trees tailored to its local requirements. This local quality approach allows optimization of clock distribution in each region independently, reducing the need for redundant global clock infrastructure across the entire device.
2Productivity
If conventional approximation or heuristic algorithms are used to solve clock placement, then computation time is reduced, but feasible solutions are often not found
Solution Approach 1:
The patent introduces an intermediary mapping layer between virtual clock regions and physical clock regions. This intermediary structure allows the optimization algorithm to work with abstract virtual regions first, then map them to physical regions, bridging the gap between computational simplicity and physical feasibility.
Solution Approach 2:
The patent performs preliminary optimization by defining virtual clock regions and their mappings before final physical placement. This preliminary action allows the algorithm to establish a feasible framework that guarantees solution validity while maintaining computational efficiency.
3Reliability
If manual floor-planning is performed to achieve feasible clock placement, then solution quality improves, but design time and effort increase significantly
Solution Approach 1:
The patent enables automated clock placement optimization that performs tasks previously requiring manual floor-planning. The system automatically defines virtual clock regions, establishes mappings to physical regions, and optimizes clock driver assignments, allowing the design tool to serve itself rather than requiring manual intervention.
Solution Approach 2:
The patent transforms the clock placement problem from a manual geometric arrangement task into an automated optimization problem by introducing virtual clock regions and mapping parameters. This parameter transformation allows automated algorithms to achieve manual-quality results without the time investment.
4Device complexity
If fixed dimensions are assigned to clock regions, then device architecture simplification is achieved, but flexibility in supporting different clock domain configurations is reduced
Solution Approach 1:
The patent introduces dynamic virtual clock regions that can be flexibly configured and mapped to physical clock regions. While physical regions maintain fixed dimensions for architectural simplicity, virtual regions can adapt their boundaries and compositions based on specific design requirements, providing flexibility without increasing physical complexity.
Data Source
AI summary
A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.