Flexible Coherent Scale-out Computing Architecture Using Integrated Photonics
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Solution Overview
Problem
Current computing architectures, particularly those based on ARM and RISC instructions, face limitations in supporting scale-out computing with coherent and non-coherent traffic due to mismatched CPU and memory interface bandwidths, and fixed I/O protocols are inadequate in addressing memory interface coherency and non-coherency issues.
Innovation Solution
The proposed solution involves a flexible computing architecture with integrated photonics links connecting compute and switch units, enabling high-speed communication and supporting both coherent and non-coherent data through a baseline protocol with user-defined extensions, using high-speed photonics links for scalable memory access and scheduling decisions over multiple wavelengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If DDR based interface is used for memory access, then memory bandwidth is improved, but it is not possible to match CPU processing capability with memory interface bandwidth
Solution Approach 1:
The patent implements dynamic bandwidth allocation where the memory interface bandwidth can be flexibly adjusted and shared among multiple CPU cores based on actual processing needs. The system dynamically configures the memory interface to match varying CPU processing capabilities rather than being fixed, allowing adaptive scaling of bandwidth allocation.
Solution Approach 2:
The memory interface is designed with multi-functionality to serve multiple CPU cores simultaneously with configurable bandwidth allocation. The same memory interface infrastructure can adapt to different processing requirements of various CPU cores, making it universally applicable across different processing scenarios without requiring dedicated interfaces for each core.
2Ease of manufacture
If fixed I/O protocol is used, then implementation simplicity is improved, but it cannot support both coherent and non-coherent traffic in scale-out architecture
Solution Approach 1:
The I/O protocol is segmented into separate coherent and non-coherent traffic handling paths. Each path has its own optimized protocol implementation, allowing the system to maintain simplicity within each segment while providing versatility across different traffic types. The segmentation enables independent optimization of each protocol path without compromising the other.
Solution Approach 2:
An intermediary protocol layer is introduced that translates between different traffic types (coherent and non-coherent) and the underlying physical interface. This intermediary handles the complexity of supporting multiple traffic types while presenting a simplified interface to higher-level protocols, effectively mediating between the need for simplicity and versatility.
3Speed
If individual main memory is provided for each SoC, then memory access speed is improved, but system complexity and cost increase in multi-node architecture
Solution Approach 1:
The patent merges memory resources across multiple SoCs by implementing a shared memory pool accessible through the fabric interconnect. Instead of each SoC having dedicated main memory, memory resources are combined and shared, reducing overall system complexity and cost while maintaining high access speeds through direct fabric connectivity to the shared memory pool.
Solution Approach 2:
The patent implements memory copying mechanisms that allow SoCs to access memory in other nodes with latency comparable to local memory access. Through the high-speed fabric interconnect, memory operations can be copied or mirrored across nodes, providing the performance characteristics of local memory while utilizing shared remote memory resources.
4Power
If photonics links are used for inter-node communication, then communication bandwidth is improved, but implementation complexity increases
Solution Approach 1:
The patent implements nested integration where photonics links are embedded within the existing electronic fabric interconnect architecture. The photonics communication infrastructure is nested inside the electronic switching fabric, allowing high-bandwidth optical communication to leverage the existing control and management planes of the electronic interconnect, thereby reducing overall implementation complexity.
Data Source
AI summary
A Method and Apparatus for Flexible Coherent and Scale-out Computing Architecture have been disclosed. In one implementation a plurality of integrated photonics are used to effect communications.